Initial import

.gitignore

@@ -0,0 +1,16 @@
+firmware/firmware.bin
+firmware/firmware.elf
+firmware/firmware.hex
+firmware/firmware.map
+testbench.exe
+testbench.vcd
+tests/*.o
+dhrystone/dhry.bin
+dhrystone/dhry.elf
+dhrystone/dhry.hex
+dhrystone/dhry.map
+dhrystone/*.d
+dhrystone/*.o
+fsm_encoding.os
+synth_vivado.log
+synth_vivado.v

Makefile

@@ -0,0 +1,37 @@
+
+TEST_OBJS=$(addsuffix .o,$(basename $(wildcard tests/*.S)))
+
+test: testbench.exe firmware/firmware.hex
+	vvp -N testbench.exe
+
+testbench.exe: testbench.v picorv32.v
+	iverilog -o testbench.exe testbench.v picorv32.v
+	chmod -x testbench.exe
+
+firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
+	python3 firmware/makehex.py $< > $@
+
+firmware/firmware.bin: firmware/firmware.elf
+	riscv64-unknown-elf-objcopy -O binary $< $@
+	chmod -x $@
+
+firmware/firmware.elf: $(TEST_OBJS) firmware/sections.lds firmware/start.S firmware/sieve.c firmware/stats.c
+	riscv64-unknown-elf-gcc -Os -m32 -march=RV32I -ffreestanding -nostdlib -o $@ \
+		-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
+		firmware/start.S firmware/sieve.c firmware/stats.c $(TEST_OBJS) -lgcc
+	chmod -x $@
+
+tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
+	riscv64-unknown-elf-gcc -m32 -march=RV32I -c -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
+		-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
+
+synth_vivado:
+	vivado -nojournal -log synth_vivado.log -mode batch -source synth_vivado.tcl
+
+clean:
+	rm -vrf $(TEST_OBJS) firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex \
+		firmware/firmware.map testbench.exe testbench.vcd .Xil fsm_encoding.os \
+		synth_vivado.log synth_vivado_*.backup.log synth_vivado.v
+
+.PHONY: test synth_vivado clean
+

README.md

@@ -0,0 +1,63 @@
+
+PicoRV32 - A Size-Optimized RISC-V CPU
+======================================
+
+PicoRV32 is a CPU core that implements the [RISC-V RV32I Instruction Set](http://riscv.org/).
+
+Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools).
+
+
+Features and Typical Applications:
+----------------------------------
+
+- Small (about 1000 LUTs in a 7-Series Xilinx FGPA)
+- High fMAX (>250 MHz on 7-Series Xilinx FGPAs)
+- Selectable native memory interface or AXI4-Lite master
+
+This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due
+to its high fMAX it can be integrated in most existing designs without crossing
+clock domains. When operated on a lower frequency, it will have a lot of timing
+slack and thus can be added to a design without compromising timing closure.
+
+For even smaller size it is possible disable support for registers `x16`..`x31` as
+well as `RDCYCLE[H]`, `RDTIME[H]`, and `RDINSTRET[H]` instructions, turning the
+processor into an RV32E core.
+
+*Note: In architectures that implement the register file in dedicated memory
+resources, such as many FPGAs, disabling the 16 upper registers may not further
+reduce the core size.*
+
+The core exists in two variations: `picorv32` and `picorv32_axi`. The former
+provides a simple native memory interface, that is easy to use in simple
+environments, and the latter provides an AXI-4 Lite Master interface that can
+easily be integrated with existing systems that are already using the AXI
+standard.
+
+A separate core `picorv32_axi_adapter` is provided to bridge between the native
+memory interface and AXI4. This core can be used to create custom cores that
+include one or more PicoRV32 cores together with local RAM, ROM, and
+memory-mapped peripherals, communicating with each other using the native
+interface, and communicating with the outside world via AXI4.
+
+
+Performance:
+------------
+
+The average Cycles per Instruction (CPI) is 6 to 8, depending on the
+application code. (Most instructions, including unconditional branches and
+not-taken conditional branches execute in 5 cycles. Memory load/store, taken
+conditional branches, JALR, and shift operations may take more than 5 cycles.)
+
+Dhrystone benchmark results: 0.124 DMIPS/MHz (219 Dhrystones/Second/MHz)
+
+*This numbers apply for setups with memory that can accomodate requests within
+one clock cycle. Slower memory will degrade the performance of the processor.*
+
+
+Todos:
+------
+
+- Optional IRQ support
+- Optional write-through cache
+- Optional support for compressed ISA
+

dhrystone/Makefile

@@ -0,0 +1,35 @@
+
+OBJS = start.o dhry_1.o dhry_2.o stdlib.o
+CFLAGS = -MD -O3 -m32 -march=RV32I -ffreestanding -nostdlib -DTIME
+
+test: testbench.exe dhry.hex
+	vvp -N testbench.exe
+
+testbench.exe: testbench.v ../picorv32.v
+	iverilog -o testbench.exe testbench.v ../picorv32.v
+	chmod -x testbench.exe
+
+dhry.hex: dhry.bin ../firmware/makehex.py
+	python3 ../firmware/makehex.py $< > $@
+
+dhry.bin: dhry.elf
+	riscv64-unknown-elf-objcopy -O binary $< $@
+	chmod -x $@
+
+dhry.elf: $(OBJS) ../firmware/sections.lds
+	riscv64-unknown-elf-gcc $(CFLAGS) -Wl,-Bstatic,-T,../firmware/sections.lds,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc
+	chmod -x $@
+
+%.o: %.c
+	riscv64-unknown-elf-gcc -c $(CFLAGS) $<
+
+%.o: %.S
+	riscv64-unknown-elf-gcc -c $(CFLAGS) $<
+
+clean:
+	rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd
+
+.PHONY: test clean
+
+-include *.d
+