Add testbench_ez

.gitignore

@@ -22,7 +22,7 @@
 /riscv-gnu-toolchain-riscv32imc
 /testbench.vvp
 /testbench_wb.vvp
-/testbench_wb.vcd
+/testbench_ez.vvp
 /testbench_sp.vvp
 /testbench_synth.vvp
 /testbench.gtkw

Makefile

@@ -25,6 +25,12 @@ test_wb: testbench_wb.vvp firmware/firmware.hex
 test_wb_vcd: testbench_wb.vvp firmware/firmware.hex
 	vvp -N $< +vcd +trace +noerror
 
+test_ez: testbench_ez.vvp
+	vvp -N $<
+
+test_ez_vcd: testbench_ez.vvp
+	vvp -N $< +vcd
+
 check: check-yices
 
 check-%: check.smt2
@@ -54,6 +60,10 @@ testbench_wb.vvp: testbench_wb.v picorv32.v
 	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
 	chmod -x $@
 
+testbench_ez.vvp: testbench_ez.v picorv32.v
+	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
+	chmod -x $@
+
 testbench_sp.vvp: testbench.v picorv32.v
 	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^
 	chmod -x $@
@@ -144,7 +154,7 @@ clean:
 		riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
 	rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
 		firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
-		testbench.vvp testbench_sp.vvp testbench_synth.vvp \
+		testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
 		testbench_wb.vvp testbench.vcd testbench.trace
 
-.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_synth download-tools build-tools toc clean
+.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean

testbench_ez.v

@@ -0,0 +1,86 @@
+// This is free and unencumbered software released into the public domain.
+//
+// Anyone is free to copy, modify, publish, use, compile, sell, or
+// distribute this software, either in source code form or as a compiled
+// binary, for any purpose, commercial or non-commercial, and by any
+// means.
+
+`timescale 1 ns / 1 ps
+
+module testbench;
+	reg clk = 1;
+	reg resetn = 0;
+	wire trap;
+
+	always #5 clk = ~clk;
+
+	initial begin
+		if ($test$plusargs("vcd")) begin
+			$dumpfile("testbench.vcd");
+			$dumpvars(0, testbench);
+		end
+		repeat (100) @(posedge clk);
+		resetn <= 1;
+		repeat (1000) @(posedge clk);
+		$finish;
+	end
+
+	wire mem_valid;
+	wire mem_instr;
+	reg mem_ready;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0] mem_wstrb;
+	reg  [31:0] mem_rdata;
+
+	always @(posedge clk) begin
+		if (mem_valid && mem_ready) begin
+			if (mem_instr)
+				$display("ifetch 0x%08x: 0x%08x", mem_addr, mem_rdata);
+			else if (mem_wstrb)
+				$display("write  0x%08x: 0x%08x (wstrb=%b)", mem_addr, mem_wdata, mem_wstrb);
+			else
+				$display("read   0x%08x: 0x%08x", mem_addr, mem_rdata);
+		end
+	end
+
+	picorv32 #(
+	) uut (
+		.clk         (clk        ),
+		.resetn      (resetn     ),
+		.trap        (trap       ),
+		.mem_valid   (mem_valid  ),
+		.mem_instr   (mem_instr  ),
+		.mem_ready   (mem_ready  ),
+		.mem_addr    (mem_addr   ),
+		.mem_wdata   (mem_wdata  ),
+		.mem_wstrb   (mem_wstrb  ),
+		.mem_rdata   (mem_rdata  )
+	);
+
+	reg [31:0] memory [0:255];
+
+	initial begin
+		memory[0] = 32'h 3fc00093; //       li      x1,1020
+		memory[1] = 32'h 0000a023; //       sw      x0,0(x1)
+		memory[2] = 32'h 0000a103; // loop: lw      x2,0(x1)
+		memory[3] = 32'h 00110113; //       addi    x2,x2,1
+		memory[4] = 32'h 0020a023; //       sw      x2,0(x1)
+		memory[5] = 32'h ff5ff06f; //       j       <loop>
+	end
+
+	always @(posedge clk) begin
+		mem_ready <= 0;
+		if (mem_valid && !mem_ready) begin
+			if (mem_addr < 1024) begin
+				mem_ready <= 1;
+				mem_rdata <= memory[mem_addr >> 2];
+				if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
+				if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
+				if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
+				if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
+			end
+			/* add memory-mapped IO here */
+		end
+	end
+endmodule

testbench_wb.v

@@ -17,7 +17,7 @@ module testbench #(
 
 	initial begin
 		if ($test$plusargs("vcd")) begin
-			$dumpfile("testbench_wb.vcd");
+			$dumpfile("testbench.vcd");
 			$dumpvars(0, testbench);
 		end
 		repeat (1000000) @(posedge clk);