Skip to content

Commit

Permalink
Revert "Merge branch 'octeontx2-af-next'"
Browse files Browse the repository at this point in the history 
This reverts commit 2ef8e39, reversing
changes made to e7ce9fc.

There are build warnings here which break the normal
build due to -Werror. Ratheesh was nice enough to quickly
follow up with fixes but didn't hit all the warnings I
see on GCC 12 so to unlock net-next from taking patches
let get this series out for now.

Link: https://lore.kernel.org/r/20220707013201.1372433-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  • Loading branch information
@kuba-moo
kuba-moo committed Jul 7, 2022
1 parent cd355d0 commit 69d7d25
Show file tree
Hide file tree
Showing 20 changed files with 67 additions and 2,876 deletions.
2 changes: 1 addition & 1 deletion drivers/net/ethernet/marvell/octeontx2/af/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,4 +11,4 @@ rvu_mbox-y := mbox.o rvu_trace.o
rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \
rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \
rvu_sdp.o rvu_npc_hash.o
rvu_sdp.o
41 changes: 6 additions & 35 deletions drivers/net/ethernet/marvell/octeontx2/af/mbox.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -169,10 +169,9 @@ M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
cgx_features_info_msg) \
M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
msg_rsp) \
M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, msg_req, msg_rsp) \
M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
cgx_mac_addr_update_rsp) \
msg_rsp) \
M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
cgx_pfc_rsp) \
/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
Expand Down Expand Up @@ -242,9 +241,6 @@ M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
npc_mcam_get_stats_req, \
npc_mcam_get_stats_rsp) \
M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key, \
npc_get_secret_key_req, \
npc_get_secret_key_rsp) \
/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
nix_lf_alloc_req, nix_lf_alloc_rsp) \
Expand Down Expand Up @@ -432,7 +428,6 @@ struct get_hw_cap_rsp {
struct mbox_msghdr hdr;
u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
u8 nix_shaping; /* Is shaping and coloring supported */
u8 npc_hash_extract; /* Is hash extract supported */
};

/* CGX mbox message formats */
Expand All @@ -456,7 +451,6 @@ struct cgx_fec_stats_rsp {
struct cgx_mac_addr_set_or_get {
struct mbox_msghdr hdr;
u8 mac_addr[ETH_ALEN];
u32 index;
};

/* Structure for requesting the operation to
Expand All @@ -472,23 +466,23 @@ struct cgx_mac_addr_add_req {
*/
struct cgx_mac_addr_add_rsp {
struct mbox_msghdr hdr;
u32 index;
u8 index;
};

/* Structure for requesting the operation to
* delete DMAC filter entry from CGX interface
*/
struct cgx_mac_addr_del_req {
struct mbox_msghdr hdr;
u32 index;
u8 index;
};

/* Structure for response against the operation to
* get maximum supported DMAC filter entries
*/
struct cgx_max_dmac_entries_get_rsp {
struct mbox_msghdr hdr;
u32 max_dmac_filters;
u8 max_dmac_filters;
};

struct cgx_link_user_info {
Expand Down Expand Up @@ -589,20 +583,10 @@ struct cgx_set_link_mode_rsp {
int status;
};

struct cgx_mac_addr_reset_req {
struct mbox_msghdr hdr;
u32 index;
};

struct cgx_mac_addr_update_req {
struct mbox_msghdr hdr;
u8 mac_addr[ETH_ALEN];
u32 index;
};

struct cgx_mac_addr_update_rsp {
struct mbox_msghdr hdr;
u32 index;
u8 index;
};

#define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
Expand Down Expand Up @@ -1456,16 +1440,6 @@ struct npc_mcam_get_stats_rsp {
u8 stat_ena; /* enabled */
};

struct npc_get_secret_key_req {
struct mbox_msghdr hdr;
u8 intf;
};

struct npc_get_secret_key_rsp {
struct mbox_msghdr hdr;
u64 secret_key[3];
};

enum ptp_op {
PTP_OP_ADJFINE = 0,
PTP_OP_GET_CLOCK = 1,
Expand Down Expand Up @@ -1648,9 +1622,6 @@ enum cgx_af_status {
LMAC_AF_ERR_PERM_DENIED = -1103,
LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
};

#endif /* MBOX_H */
25 changes: 0 additions & 25 deletions drivers/net/ethernet/marvell/octeontx2/af/npc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,14 +10,6 @@

#define NPC_KEX_CHAN_MASK 0xFFFULL

#define SET_KEX_LD(intf, lid, ltype, ld, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)

#define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \
rvu_write64(rvu, blkaddr, \
NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)

enum NPC_LID_E {
NPC_LID_LA = 0,
NPC_LID_LB,
Expand Down Expand Up @@ -208,7 +200,6 @@ enum key_fields {
NPC_ERRLEV,
NPC_ERRCODE,
NPC_LXMB,
NPC_EXACT_RESULT,
NPC_LA,
NPC_LB,
NPC_LC,
Expand Down Expand Up @@ -389,22 +380,6 @@ struct nix_rx_action {
#endif
};

/* NPC_AF_INTFX_KEX_CFG field masks */
#define NPC_EXACT_NIBBLE_START 40
#define NPC_EXACT_NIBBLE_END 43
#define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40)

/* NPC_EXACT_KEX_S nibble definitions for each field */
#define NPC_EXACT_NIBBLE_HIT BIT_ULL(40)
#define NPC_EXACT_NIBBLE_OPC BIT_ULL(40)
#define NPC_EXACT_NIBBLE_WAY BIT_ULL(40)
#define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41)

#define NPC_EXACT_RESULT_HIT BIT_ULL(0)
#define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1)
#define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3)
#define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5)

/* NPC_AF_INTFX_KEX_CFG field masks */
#define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)

Expand Down
5 changes: 2 additions & 3 deletions drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -155,7 +155,7 @@

/* Rx parse key extract nibble enable */
#define NPC_PARSE_NIBBLE_INTF_RX (NPC_PARSE_NIBBLE_CHAN | \
NPC_PARSE_NIBBLE_L2L3_BCAST | \
NPC_PARSE_NIBBLE_ERRCODE | \
NPC_PARSE_NIBBLE_LA_LTYPE | \
NPC_PARSE_NIBBLE_LB_LTYPE | \
NPC_PARSE_NIBBLE_LC_LTYPE | \
Expand Down Expand Up @@ -15123,8 +15123,7 @@ static struct npc_mcam_kex npc_mkex_default = {
.kpu_version = NPC_KPU_PROFILE_VER,
.keyx_cfg = {
/* nibble: LA..LE (ltype only) + Error code + Channel */
[NIX_INTF_RX] = ((u64)NPC_MCAM_KEY_X2 << 32) | NPC_PARSE_NIBBLE_INTF_RX |
(u64)NPC_EXACT_NIBBLE_HIT,
[NIX_INTF_RX] = ((u64)NPC_MCAM_KEY_X2 << 32) | NPC_PARSE_NIBBLE_INTF_RX,
/* nibble: LA..LE (ltype only) */
[NIX_INTF_TX] = ((u64)NPC_MCAM_KEY_X2 << 32) | NPC_PARSE_NIBBLE_INTF_TX,
},
Expand Down
16 changes: 0 additions & 16 deletions drivers/net/ethernet/marvell/octeontx2/af/rvu.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@
#include "ptp.h"

#include "rvu_trace.h"
#include "rvu_npc_hash.h"

#define DRV_NAME "rvu_af"
#define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
Expand Down Expand Up @@ -69,8 +68,6 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu)
hw->cap.nix_tx_link_bp = true;
hw->cap.nix_rx_multicast = true;
hw->cap.nix_shaper_toggle_wait = false;
hw->cap.npc_hash_extract = false;
hw->cap.npc_exact_match_enabled = false;
hw->rvu = rvu;

if (is_rvu_pre_96xx_C0(rvu)) {
Expand All @@ -88,9 +85,6 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu)

if (!is_rvu_otx2(rvu))
hw->cap.per_pf_mbox_regs = true;

if (is_rvu_npc_hash_extract_en(rvu))
hw->cap.npc_hash_extract = true;
}

/* Poll a RVU block's register 'offset', for a 'zero'
Expand Down Expand Up @@ -1128,12 +1122,6 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
goto cgx_err;
}

err = rvu_npc_exact_init(rvu);
if (err) {
dev_err(rvu->dev, "failed to initialize exact match table\n");
return err;
}

/* Assign MACs for CGX mapped functions */
rvu_setup_pfvf_macaddress(rvu);

Expand Down Expand Up @@ -2003,7 +1991,6 @@ int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,

rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
rsp->nix_shaping = hw->cap.nix_shaping;
rsp->npc_hash_extract = hw->cap.npc_hash_extract;

return 0;
}
Expand Down Expand Up @@ -2561,9 +2548,6 @@ static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)

static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
{
if (rvu_npc_exact_has_match_table(rvu))
rvu_npc_exact_reset(rvu, pcifunc);

mutex_lock(&rvu->flr_lock);
/* Reset order should reflect inter-block dependencies:
* 1. Reset any packet/work sources (NIX, CPT, TIM)
Expand Down
24 changes: 1 addition & 23 deletions drivers/net/ethernet/marvell/octeontx2/af/rvu.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -338,8 +338,6 @@ struct hw_cap {
bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
bool programmable_chans; /* Channels programmable ? */
bool ipolicer;
bool npc_hash_extract; /* Hash extract enabled ? */
bool npc_exact_match_enabled; /* Exact match supported ? */
};

struct rvu_hwinfo {
Expand Down Expand Up @@ -371,7 +369,6 @@ struct rvu_hwinfo {
struct rvu *rvu;
struct npc_pkind pkind;
struct npc_mcam mcam;
struct npc_exact_table *table;
};

struct mbox_wq_info {
Expand Down Expand Up @@ -422,7 +419,6 @@ struct npc_kpu_profile_adapter {
const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
const struct npc_kpu_profile *kpu; /* array[kpus] */
struct npc_mcam_kex *mkex;
struct npc_mcam_kex_hash *mkex_hash;
bool custom;
size_t pkinds;
size_t kpus;
Expand Down Expand Up @@ -579,17 +575,6 @@ static inline bool is_rvu_otx2(struct rvu *rvu)
midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
}

static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
{
u64 npc_const3;

npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
if (!(npc_const3 & BIT_ULL(62)))
return false;

return true;
}

static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
u8 lmacid, u8 chan)
{
Expand Down Expand Up @@ -769,6 +754,7 @@ u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
u32 convert_bytes_to_dwrr_mtu(u32 bytes);

/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
void rvu_npc_freemem(struct rvu *rvu);
int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
Expand All @@ -787,17 +773,14 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
u64 chan);
void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
bool enable);

void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
int nixlf, int type, bool enable);
void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
int group, int alg_idx, int mcam_index);

void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
int blkaddr, int *alloc_cnt,
int *enable_cnt);
Expand Down Expand Up @@ -832,11 +815,6 @@ int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
int type);
bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
int index);
int rvu_npc_init(struct rvu *rvu);
int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
u64 bcast_mcast_val, u64 bcast_mcast_mask);
void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);

/* CPT APIs */
int rvu_cpt_register_interrupts(struct rvu *rvu);
Expand Down
Loading

0 comments on commit 69d7d25

Please sign in to comment.