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Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versa…
…clock' into clk-next - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - Support for Renesas VersaClock7 clock generator family * clk-baikal: clk: baikal-t1: Convert to platform device driver clk: baikal-t1: Add DDR/PCIe directly controlled resets support dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs clk: baikal-t1: Move reset-controls code into a dedicated module clk: baikal-t1: Add SATA internal ref clock buffer clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent clk: baikal-t1: Fix invalid xGMAC PTP clock divider clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD * clk-broadcom: clk: bcm: rpi: Add support for VEC clock clk: bcm: rpi: Handle pixel clock in firmware clk: bcm: rpi: Add support HEVC clock clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration clk: bcm2835: Round UART input clock up clk: bcm2835: Make peripheral PLLC critical * clk-vc5: clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: vc5: Use regmap_{set,clear}_bits() where appropriate clk: vc5: Check IO access results * clk-versaclock: clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings
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Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Renesas Versaclock7 Programmable Clock Device Tree Bindings | ||
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maintainers: | ||
- Alex Helms <alexander.helms.jy@renesas.com> | ||
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description: | | ||
Renesas Versaclock7 is a family of configurable clock generator and | ||
jitter attenuator ICs with fractional and integer dividers. | ||
properties: | ||
'#clock-cells': | ||
const: 1 | ||
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compatible: | ||
enum: | ||
- renesas,rc21008a | ||
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reg: | ||
maxItems: 1 | ||
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clocks: | ||
items: | ||
- description: External crystal or oscillator | ||
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clock-names: | ||
items: | ||
- const: xin | ||
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required: | ||
- '#clock-cells' | ||
- compatible | ||
- reg | ||
- clocks | ||
- clock-names | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
vc7_xin: clock { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <49152000>; | ||
}; | ||
i2c@0 { | ||
reg = <0x0 0x100>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
vc7: clock-controller@9 { | ||
compatible = "renesas,rc21008a"; | ||
reg = <0x9>; | ||
#clock-cells = <1>; | ||
clocks = <&vc7_xin>; | ||
clock-names = "xin"; | ||
}; | ||
}; |
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# SPDX-License-Identifier: GPL-2.0-only | ||
obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o | ||
obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o | ||
obj-$(CONFIG_CLK_BT1_CCU_RST) += ccu-rst.o |
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