Proposed RISC-V Composable Custom Extensions Specification

assignment1

A tiny C header-only risc-v emulator.

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

Free collection of hardware modules written in Verilog for FPGAs and embedded systems.

RISC-V System on Chip Template

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Latest in the line of the E32 processors with better/generic cache placement

192-bit prime field multiplier

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Hardware implementation of the SHA256 algorithm using AXI bus interconnect on the Xilinx Artix 7 (Basys 3 development board).

The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.

An acceleration engine for proving SNARKS over the bn128 curve, targeted for AWS FPGAs

A project for managing all Pop!_OS sources

4 stage, in-order, secure RISC-V core based on the CV32E40P

Implementation of entire RISC-V ISA using Verilog to run on FPGA

Build NVIDIA® CUDA™ code for OpenCL™ 1.2 devices

RISC-V Assembly Language Programming

Simple, zero-copy DMA to/from userspace.

FPGA project for rotating AXI stream images.

minimal code to access ps DDR from PL

bachelor thesis about PS-PL Communication on a SoC. Working on the MicroZed-Board with Vivado and PetaLinux.

Driving 32BY16 RGB Panel using ZYNQ SoC

Video Processing SoC on ZebBoard

GPS NMEA Library for stm32 LL