OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

SystemVerilog compiler and language services

Test suite designed to check compliance with the SystemVerilog standard.

The next best thing after Bloomberg Terminal

Next generation cosa.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Reads a state transition system and performs property checking

Headless recorder is a Chrome extension that records your browser interactions and generates a Puppeteer or Playwright script.

Tools for working with LTLf and automata.

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

SystemVerilog code for image processing tasks like demosaicing

Random number generators such as LFSRs, LHCAs

Utilities for clock-domain crossing with an FPGA

Generate a gray code of arbitrary width in SystemVerilog

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Fully featured implementation of Inter-IC (I2C) bus master for FPGAs

🏡 Open source home automation that puts local control and privacy first

Package manager and build abstraction tool for FPGA/ASIC development

⚡High Performance DICOM Medical Image Parser in Go.

Bus bridges and other odds and ends

Build Customized FPGA Implementations for Vivado

Duktape - embeddable Javascript engine with a focus on portability and compact footprint

A port of Node.JS with far lower system requirements. Community version for POSIX systems such as Linux, uClinux or Mac OS X.