Register Formatter - Generate SVG diagrams of control register-style data formats

RISC-V IOMMU Specification

Documentation developer guide

Instruction Set Generator initially contributed by Futurewei

chroot, mount --bind, and binfmt_misc without privilege/setup for Linux

Python Model of the RISC-V ISA

IEEE754 reduced reduced precision floating point

RISC-V architecture concurrency model litmus tests

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Sail RISC-V model

Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

RISC-V RV64GC emulator designed for RTL co-simulation

A utility for processing command line arguments

Devicetree Specification document source files

RISC-V SMBIOS Type 44 Spec

Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.

musl libc for RISC-V

PLIC Specification

A RISC-V ELF psABI Document

Working draft of the proposed RISC-V V vector extension

Fork of OpenOCD that has RISC-V support

RISC-V Assembly Programmer's Manual

Locus site for Public Review of Several RISC-V ISA Formal Specs

a fast, scalable, multi-language and extensible build system

Environment Modules: provides dynamic modification of a user's environment

Working draft of the proposed RISC-V Bitmanipulation extension

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.