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Config files for my GitHub profile.

Verilog 2 Updated Sep 15, 2021

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Batchfile 422 85 Updated Sep 14, 2023

FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Verilog 28 7 Updated Jul 4, 2024

SpikingJelly is an open-source deep learning framework for Spiking Neural Network (SNN) based on PyTorch.

Python 1,318 237 Updated Aug 9, 2024

Deep and online learning with spiking neural networks in Python

Python 1,280 217 Updated Aug 7, 2024

ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.

Verilog 155 48 Updated Apr 20, 2019
Python 44 14 Updated Jul 28, 2020
Verilog 81 47 Updated Nov 7, 2019

Must-have verilog systemverilog modules

Verilog 1,612 373 Updated Jul 6, 2024

Multi-port BRAM IP for ASIC and FPGA

SystemVerilog 11 3 Updated Apr 21, 2021

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog 246 75 Updated Apr 30, 2024

N bit Parallel Prefix Adder using Verilog HDL

Verilog 2 1 Updated Nov 27, 2019

SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset is divided into several chunks that are processed during seve…

VHDL 21 1 Updated May 26, 2022

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key exp…

Verilog 18 3 Updated Apr 15, 2021

IC implementation of Systolic Array for TPU

Verilog 139 23 Updated Mar 4, 2024

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) h…

Verilog 33 1 Updated Dec 3, 2023

All in one vscode plugin for HDL development

Verilog 377 11 Updated Sep 30, 2024

deep learning for image processing including classification and object-detection etc.

Python 22,580 7,930 Updated Jul 25, 2024

网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR

Verilog 54 9 Updated Jul 20, 2023

🔥🔥🔥 A collection of some awesome public CUDA, cuBLAS, TensorRT and High Performance Computing (HPC) projects.

145 18 Updated Sep 3, 2024

Some Code for Master Thesis - Research on Deep Learning Based Modulation Recognition Technologies

Python 187 58 Updated Nov 9, 2019

JDMR-Net: Joint Detection and Modulation Recognition Networks for LPI Radar Signals

11 Updated May 24, 2023

SystemVerilog to Verilog conversion

Haskell 540 52 Updated Sep 29, 2024

Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.

Verilog 1 Updated Sep 21, 2021

FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。

SystemVerilog 84 16 Updated Sep 18, 2024

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器,可实现高压缩率的无损/近无损图像压缩。

Verilog 199 38 Updated Sep 18, 2024