target-ppc: convert lscbx instruction to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc/helper.h

@@ -15,6 +15,8 @@ DEF_HELPER_3(stsw, void, tl, i32, i32)
 DEF_HELPER_1(dcbz, void, tl)
 DEF_HELPER_1(dcbz_970, void, tl)
 DEF_HELPER_1(icbi, void, tl)
+DEF_HELPER_4(lscbx, tl, tl, i32, i32, i32)
+
 
 DEF_HELPER_2(fcmpo, i32, i64, i64)
 DEF_HELPER_2(fcmpu, i32, i64, i64)

target-ppc/op_helper.c

@@ -24,21 +24,6 @@
 #include "helper_regs.h"
 #include "op_helper.h"
 
-#define MEMSUFFIX _raw
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#if !defined(CONFIG_USER_ONLY)
-#define MEMSUFFIX _user
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#define MEMSUFFIX _kernel
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#define MEMSUFFIX _hypv
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#endif
-
 //#define DEBUG_OP
 //#define DEBUG_EXCEPTIONS
 //#define DEBUG_SOFTWARE_TLB
@@ -329,6 +314,45 @@ void helper_icbi(target_ulong addr)
     tb_invalidate_page_range(addr, addr + env->icache_line_size);
 }
 
+// XXX: to be tested
+target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
+{
+    int i, c, d;
+#ifdef CONFIG_USER_ONLY
+#define ldfun ldub_raw
+#else
+    int (*ldfun)(target_ulong);
+
+    switch (env->mmu_idx) {
+    default:
+    case 0: ldfun = ldub_user;
+        break;
+    case 1: ldfun = ldub_kernel;
+        break;
+    case 2: ldfun = ldub_hypv;
+        break;
+    }
+#endif
+    d = 24;
+    for (i = 0; i < xer_bc; i++) {
+        c = ldfun((uint32_t)addr++);
+        /* ra (if not 0) and rb are never modified */
+        if (likely(reg != rb && (ra == 0 || reg != ra))) {
+            env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
+        }
+        if (unlikely(c == xer_cmp))
+            break;
+        if (likely(d != 0)) {
+            d -= 8;
+        } else {
+            d = 24;
+            reg++;
+            reg = reg & 0x1F;
+        }
+    }
+    return i;
+}
+
 /*****************************************************************************/
 /* Fixed point operations helpers */
 #if defined(TARGET_PPC64)

target-ppc/op_helper.h

@@ -18,17 +18,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#if defined(MEMSUFFIX)
-
-/* Memory load/store helpers */
-void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb);
-void glue(do_POWER2_lfq, MEMSUFFIX) (void);
-void glue(do_POWER2_lfq_le, MEMSUFFIX) (void);
-void glue(do_POWER2_stfq, MEMSUFFIX) (void);
-void glue(do_POWER2_stfq_le, MEMSUFFIX) (void);
-
-#else
-
 void do_print_mem_EA (target_ulong EA);
 
 /* Registers load and stores */
@@ -94,5 +83,3 @@ void do_440_dlmzb (void);
 void do_load_403_pb (int num);
 void do_store_403_pb (int num);
 #endif
-
-#endif

target-ppc/op_mem.h

@@ -303,15 +303,4 @@ void OPPROTO glue(op_ecowx_le_64, MEMSUFFIX) (void)
 }
 #endif
 
-/* XXX: those micro-ops need tests ! */
-/* PowerPC 601 specific instructions (POWER bridge) */
-void OPPROTO glue(op_POWER_lscbx, MEMSUFFIX) (void)
-{
-    /* When byte count is 0, do nothing */
-    if (likely(T1 != 0)) {
-        glue(do_POWER_lscbx, MEMSUFFIX)(PARAM1, PARAM2, PARAM3);
-    }
-    RETURN();
-}
-
 #undef MEMSUFFIX

target-ppc/translate.c

@@ -4526,47 +4526,26 @@ GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
-/* As lscbx load from memory byte after byte, it's always endian safe.
- * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
- */
-#define op_POWER_lscbx(start, ra, rb)                                         \
-(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
-#define gen_op_POWER_lscbx_64_raw       gen_op_POWER_lscbx_raw
-#define gen_op_POWER_lscbx_64_user      gen_op_POWER_lscbx_user
-#define gen_op_POWER_lscbx_64_kernel    gen_op_POWER_lscbx_kernel
-#define gen_op_POWER_lscbx_64_hypv      gen_op_POWER_lscbx_hypv
-#define gen_op_POWER_lscbx_le_raw       gen_op_POWER_lscbx_raw
-#define gen_op_POWER_lscbx_le_user      gen_op_POWER_lscbx_user
-#define gen_op_POWER_lscbx_le_kernel    gen_op_POWER_lscbx_kernel
-#define gen_op_POWER_lscbx_le_hypv      gen_op_POWER_lscbx_hypv
-#define gen_op_POWER_lscbx_le_64_raw    gen_op_POWER_lscbx_raw
-#define gen_op_POWER_lscbx_le_64_user   gen_op_POWER_lscbx_user
-#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
-#define gen_op_POWER_lscbx_le_64_hypv   gen_op_POWER_lscbx_hypv
-static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
-    GEN_MEM_FUNCS(POWER_lscbx),
-};
-
 /* lscbx - lscbx. */
 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
 {
-    int ra = rA(ctx->opcode);
-    int rb = rB(ctx->opcode);
+    TCGv t0 = tcg_temp_new();
+    TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
+    TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
+    TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
 
-    gen_addr_reg_index(cpu_T[0], ctx);
-    if (ra == 0) {
-        ra = rb;
-    }
+    gen_addr_reg_index(t0, ctx);
     /* NIP cannot be restored if the memory exception comes from an helper */
     gen_update_nip(ctx, ctx->nip - 4);
-    tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
-    tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
-    tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
-    op_POWER_lscbx(rD(ctx->opcode), ra, rb);
+    gen_helper_lscbx(t0, t0, t1, t2, t3);
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t3);
     tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
-    tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
+    tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
     if (unlikely(Rc(ctx->opcode) != 0))
-        gen_set_Rc0(ctx, cpu_T[0]);
+        gen_set_Rc0(ctx, t0);
+    tcg_temp_free(t0);
 }
 
 /* maskg - maskg. */