Skip to content

Commit

Permalink
Merge tag 'arm-fixes-6.11-3' of git://git.kernel.org/pub/scm/linux/ke…
Browse files Browse the repository at this point in the history
…rnel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "The bulk of the changes this time are for device tree files in the
  rockchips platform, addressing correctness issues on individual
  boards, plus one change in the rk356x SoC file to make it match the
  binding.

  The only other changes that came in are

   - a CPU frequencey scaling fix for JH7110 (RISC-V)

   - a build fix for the cznic hwrandom driver

   - a fix for a deadlock in qualcomm uefi secure application firmware
     driver"

* tag 'arm-fixes-6.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  platform: cznic: turris-omnia-mcu: fix HW_RANDOM dependency
  riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
  firmware: qcom: uefisecapp: Fix deadlock in qcuefi_acquire()
  arm64: dts: rockchip: Fix compatibles for RK3588 VO{0,1}_GRF
  dt-bindings: soc: rockchip: Fix compatibles for RK3588 VO{0,1}_GRF
  arm64: dts: rockchip: override BIOS_DISABLE signal via GPIO hog on RK3399 Puma
  arm64: dts: rockchip: fix eMMC/SPI corruption when audio has been used on RK3399 Puma
  arm64: dts: rockchip: fix PMIC interrupt pin in pinctrl for ROCK Pi E
  arm64: dts: rockchip: Remove broken tsadc pinctrl binding for rk356x
  • Loading branch information
torvalds committed Sep 11, 2024
2 parents 3857c7b + 0e7af99 commit 77f5878
Show file tree
Hide file tree
Showing 8 changed files with 60 additions and 13 deletions.
10 changes: 9 additions & 1 deletion Documentation/devicetree/bindings/soc/rockchip/grf.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,16 @@ properties:
- rockchip,rk3588-pcie3-pipe-grf
- rockchip,rk3588-usb-grf
- rockchip,rk3588-usbdpphy-grf
- rockchip,rk3588-vo-grf
- rockchip,rk3588-vo0-grf
- rockchip,rk3588-vo1-grf
- rockchip,rk3588-vop-grf
- rockchip,rv1108-usbgrf
- const: syscon
- items:
- const: rockchip,rk3588-vo-grf
- const: syscon
deprecated: true
description: Use rockchip,rk3588-vo{0,1}-grf instead.
- items:
- enum:
- rockchip,px30-grf
Expand Down Expand Up @@ -262,6 +268,8 @@ allOf:
contains:
enum:
- rockchip,rk3588-vo-grf
- rockchip,rk3588-vo0-grf
- rockchip,rk3588-vo1-grf

then:
required:
Expand Down
2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
Original file line number Diff line number Diff line change
Expand Up @@ -387,7 +387,7 @@

pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};

Expand Down
36 changes: 33 additions & 3 deletions arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -154,6 +154,22 @@
};
};

&gpio3 {
/*
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
* eMMC and SPI flash powered-down initially (in fact it keeps the
* reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to override
* that signal so that eMMC and SPI can be used regardless of the state
* of the signal.
*/
bios-disable-override-hog {
gpios = <RK_PD5 GPIO_ACTIVE_LOW>;
gpio-hog;
line-name = "bios_disable_override";
output-high;
};
};

&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
Expand Down Expand Up @@ -409,6 +425,7 @@

&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
Expand All @@ -417,8 +434,8 @@
/*
* As Q7 does not specify neither a global nor a RX clock for I2S these
* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
* Therefore we have to redefine the i2s0_2ch_bus definition to prevent
* conflicts.
* Therefore we have to redefine the i2s0_2ch_bus and i2s0_2ch_bus_bclk_off
* definitions to prevent conflicts.
*/
&i2s0_2ch_bus {
rockchip,pins =
Expand All @@ -428,6 +445,14 @@
<3 RK_PD7 1 &pcfg_pull_none>;
};

&i2s0_2ch_bus_bclk_off {
rockchip,pins =
<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>;
};

&io_domains {
status = "okay";
bt656-supply = <&vcc_1v8>;
Expand All @@ -449,9 +474,14 @@

&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&q7_thermal_pin>;
pinctrl-0 = <&q7_thermal_pin &bios_disable_override_hog_pin>;

gpios {
bios_disable_override_hog_pin: bios-disable-override-hog-pin {
rockchip,pins =
<3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
};

q7_thermal_pin: q7-thermal-pin {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
Expand Down
7 changes: 3 additions & 4 deletions arch/arm64/boot/dts/rockchip/rk356x.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -1592,10 +1592,9 @@
<&cru SRST_TSADCPHY>;
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&tsadc_pin>;
pinctrl-1 = <&tsadc_shutorg>;
pinctrl-2 = <&tsadc_pin>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&tsadc_shutorg>;
pinctrl-1 = <&tsadc_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -582,14 +582,14 @@
};

vo0_grf: syscon@fd5a6000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
compatible = "rockchip,rk3588-vo0-grf", "syscon";
reg = <0x0 0xfd5a6000 0x0 0x2000>;
clocks = <&cru PCLK_VO0GRF>;
};

vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
compatible = "rockchip,rk3588-vo1-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x4000>;
clocks = <&cru PCLK_VO1GRF>;
};

Expand Down
6 changes: 6 additions & 0 deletions arch/riscv/boot/dts/starfive/jh7110-common.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -365,6 +365,12 @@
};
};

&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
<&pllclk JH7110_PLLCLK_PLL0_OUT>;
assigned-clock-rates = <500000000>, <1500000000>;
};

&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
Expand Down
4 changes: 4 additions & 0 deletions drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
Original file line number Diff line number Diff line change
Expand Up @@ -715,6 +715,10 @@ static int qcuefi_set_reference(struct qcuefi_client *qcuefi)
static struct qcuefi_client *qcuefi_acquire(void)
{
mutex_lock(&__qcuefi_lock);
if (!__qcuefi) {
mutex_unlock(&__qcuefi_lock);
return NULL;
}
return __qcuefi;
}

Expand Down
2 changes: 1 addition & 1 deletion drivers/platform/cznic/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ config TURRIS_OMNIA_MCU_TRNG
bool "Turris Omnia MCU true random number generator"
default y
depends on TURRIS_OMNIA_MCU_GPIO
depends on HW_RANDOM
depends on HW_RANDOM=y || HW_RANDOM=TURRIS_OMNIA_MCU
help
Say Y here to add support for the true random number generator
provided by CZ.NIC's Turris Omnia MCU.
Expand Down

0 comments on commit 77f5878

Please sign in to comment.