Fixes

lisphacker · Oct 25, 2023 · 2bba0b1 · 2bba0b1
1 parent f7aadbd
commit 2bba0b1
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Showing 3 changed files with 11 additions and 6 deletions.
diff --git a/build.sh b/build.sh
@@ -1,3 +1,3 @@
 #!/bin/bash
 
-stack build --pedantic 2>&1 | tee build.log
+stack build 2>&1 | tee build.log
diff --git a/src/TIS100/Tiles/T21.hs b/src/TIS100/Tiles/T21.hs
@@ -150,11 +150,14 @@ instance IsConnectedTile T21 where
 
   writeValueTo = setPortVal False -- External call
 
-  step t = case (runState . tileState) t of
-    Ready -> stepReady
-    WaitingOnRead _ Nothing -> t
-    WaitingOnRead _ (Just _) -> stepReady
-    WaitingOnWrite _ _ -> t
+  step t =
+    if null (tileProgram t)
+      then t
+      else case (runState . tileState) t of
+        Ready -> stepReady
+        WaitingOnRead _ Nothing -> t
+        WaitingOnRead _ (Just _) -> stepReady
+        WaitingOnWrite _ _ -> t
    where
     stepReady :: T21
     stepReady = stepReady'

diff --git a/tissim/Main.hs b/tissim/Main.hs
@@ -17,6 +17,8 @@ main = do
   print asm
 
   let initialCPUState = CPU.createInitialCPUState cfg asm
+  print initialCPUState
+
   finalSimState <- case initialCPUState of
     Left err -> error $ show err
     Right cpuState -> Run.run $ Run.SimState cpuState (ParserCfg.inputs cfg) (ParserCfg.outputs cfg)