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lisphacker committed Oct 10, 2023
1 parent 85caca7 commit a5a79db
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Showing 4 changed files with 49 additions and 11 deletions.
1 change: 1 addition & 0 deletions examples/segment00150/segment00150.asm
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@@ -1,4 +1,5 @@
@0
ADD 10
MOV UP, DOWN
@4
MOV UP, DOWN
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3 changes: 2 additions & 1 deletion run_tests.sh
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@@ -1,3 +1,4 @@
#!/bin/bash

stack run tissim -- examples/segment00150/segment00150.asm -c examples/segment00150/segment00150.cfg
./build.sh
stack run tissim -- examples/segment00150/segment00150.asm -c examples/segment00150/segment00150.cfg 2>&1 | tee test.log
18 changes: 12 additions & 6 deletions sim/Main.hs
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@@ -1,11 +1,14 @@
module Main where

import CmdLine (CmdLineOpts (..), ConfigSource (..), parseCmdLine)
import Control.Monad (foldM, replicateM)
import Data.Either (fromRight)
import qualified Data.Vector as V
import TIS100.Parser.AsmParser (AsmSource, parseAsm)
import TIS100.Parser.Config (Config (..))
import TIS100.Parser.ConfigParser (parseConfig, readExternalInputs)
import TIS100.Sim.CPU (createInitialCPUState)
import TIS100.Sim.Run (SimState (SimState), runStep)
import qualified TIS100.Sim.CPU as CPU
import qualified TIS100.Sim.Run as Run

readConfig :: CmdLineOpts -> IO Config
readConfig cmdLineOpts = do
Expand Down Expand Up @@ -39,16 +42,19 @@ main = do
asm <- readAsm cmdLineOpts
print asm

let initialCPUState = createInitialCPUState cfg asm
let initialCPUState = CPU.createInitialCPUState cfg asm

print ""
print initialCPUState
-- print initialCPUState
print $ V.head . CPU.tiles <$> initialCPUState

nextSimState <- case initialCPUState of
Left err -> error $ show err
Right cpuState -> runStep $ SimState cpuState (inputs cfg) (outputs cfg)
-- Right cpuState -> Run.SimState cpuState (inputs cfg) (outputs cfg) >>= (replicateM 20 . Run.runStep)
Right cpuState -> foldM (\s i -> Run.runStep s) (Run.SimState cpuState (inputs cfg) (outputs cfg)) [1 .. 20]

print ""
print nextSimState
print $ V.head . CPU.tiles . Run.cpu $ nextSimState
-- print $ V.head . CPU.tiles . Run.cpu $ nextSimStates !! 19

return ()
38 changes: 34 additions & 4 deletions src/TIS100/Sim/Run.hs
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Expand Up @@ -2,6 +2,7 @@ module TIS100.Sim.Run where

import Control.Monad (foldM)
import Control.Monad.ST
import Data.IntMap qualified as IM
import Data.Maybe (fromJust, fromMaybe)
import Data.Vector qualified as MV
import Data.Vector qualified as V
Expand All @@ -28,6 +29,21 @@ type RWTileVector = MV.MVector RealWorld CPU.PositionedTile
runStep :: SimState -> IO SimState
runStep = processComm >> stepTiles

readInputValue :: Int -> CFG.IODef -> IO (Maybe Int, CFG.IODef)
readInputValue ti iodef = case IM.lookup ti iodef of
Just (CFG.List (v : vs)) -> return (Just v, IM.insert ti (CFG.List vs) iodef)
Just (CFG.List []) -> return (Nothing, iodef)
Just (CFG.File fp) -> return (Nothing, iodef)
Just (CFG.StdIO) -> return (Nothing, iodef)
Nothing -> return (Nothing, iodef)

writeOutputValue :: Int -> Int -> CFG.IODef -> IO CFG.IODef
writeOutputValue ti v iodef = case IM.lookup ti iodef of
Just (CFG.List vs) -> return $ IM.insert ti (CFG.List (vs ++ [v])) iodef
Just (CFG.File fp) -> return $ iodef
Just (CFG.StdIO) -> return $ iodef
Nothing -> return $ iodef

processComm :: SimState -> IO SimState
processComm (SimState (CPU.CPUState (CPU.CPUConfig rows cols) tiles) ins outs) = do
mtiles <- V.thaw tiles
Expand All @@ -44,8 +60,15 @@ processComm (SimState (CPU.CPUState (CPU.CPUConfig rows cols) tiles) ins outs) =

case getRunState tile of
Tiles.WaitingOnRead p -> do
if r == 0
then return (tiles, ins, outs)
if r == 0 && p == Tiles.UP
then do
(maybeV, ins') <- readInputValue i ins
case maybeV of
Just v -> do
let tile' = writeValueTo p (Tiles.Value v) tile
MV.write tiles i $ ptile{CPU.tile = tile'}
return (tiles, ins', outs)
Nothing -> return (tiles, ins', outs)
else do
let o = getOtherTile i p
optile <- MV.read tiles o
Expand All @@ -60,8 +83,15 @@ processComm (SimState (CPU.CPUState (CPU.CPUConfig rows cols) tiles) ins outs) =
return (tiles, ins, outs)
else return (tiles, ins, outs)
Tiles.WaitingOnWrite p -> do
if r == rows - 1
then return (tiles, ins, outs)
if r == rows - 1 && p == Tiles.DOWN
then do
let (tile', maybeV) = readValueFrom p tile
case maybeV of
Just (Tiles.Value v) -> do
outs' <- writeOutputValue i v outs
MV.write tiles i $ ptile{CPU.tile = tile'}
return (tiles, ins, outs')
Nothing -> return (tiles, ins, outs)
else do
let o = getOtherTile i p
optile <- MV.read tiles o
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