Remove support for 3DNow!, both intrinsics and builtins. #96246
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This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. Support for the underlying LLVM intrinsics remains, for the moment. They will be removed in a future patch. (Originally uploaded in https://reviews.llvm.org/D94213) Works towards issue llvm#41665.
This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. Works towards issue llvm#41665.
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@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-clang-driver Author: James Y Knight (jyknight) ChangesRemove support for 3DNow!, both intrinsics and builtins. This set of instructions was only supported by AMD chips starting in This is being done as a predecessor towards general removal of MMX (Clang half originally uploaded in https://reviews.llvm.org/D94213) Works towards issue #41665. Patch is 130.16 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/96246.diff 32 Files Affected:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 36e23981cc5df..cfe3526283d69 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -936,6 +936,23 @@ X86 Support
^^^^^^^^^^^
- Remove knl/knm specific ISA supports: AVX512PF, AVX512ER, PREFETCHWT1
+- Support has been removed for the AMD "3DNow!" instruction-set.
+ Neither modern AMD CPUs, nor any Intel CPUs implement these
+ instructions, and they were never widely used.
+ * The options ``-m3dnow`` and ``-m3dnowa`` are no longer honored, and will emit a warning if used.
+ * The macros ``__3dNOW__`` and ``__3dNOW_A__`` are no longer ever set by the compiler.
+ * The header ``<mm3dnow.h>`` still exists, but all of the the 3dNow
+ intrinsic functions have been removed: ``_m_femms``,
+ ``_m_pavgusb``, ``_m_pf2id``, ``_m_pfacc``, ``_m_pfadd``,
+ ``_m_pfcmpeq``, ``_m_pfcmpge``, ``_m_pfcmpgt``, ``_m_pfmax``,
+ ``_m_pfmin``, ``_m_pfmul``, ``_m_pfrcp``, ``_m_pfrcpit1``,
+ ``_m_pfrcpit2``, ``_m_pfrsqrt``, ``_m_pfrsqrtit1``, ``_m_pfsub``,
+ ``_m_pfsubr``, ``_m_pi2fd``, ``_m_pmulhrw``, ``_m_pf2iw``,
+ ``_m_pfnacc``, ``_m_pfpnacc``, ``_m_pi2fw``, ``_m_pswapdsf``,
+ ``_m_pswapdsi``
+ * The compiler builtins (``__builtin_ia32_femms``, and so on)
+ corresponding to each of the above intrinsics have been removed.
+
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def
index 7074479786b97..a85e7918f4d7e 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -37,36 +37,6 @@ TARGET_BUILTIN(__builtin_ia32_undef512, "V8d", "ncV:512:", "")
TARGET_BUILTIN(__builtin_ia32_readeflags_u32, "Ui", "n", "")
TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "")
-// 3DNow!
-//
-TARGET_BUILTIN(__builtin_ia32_femms, "v", "n", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pavgusb, "V8cV8cV8c", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pf2id, "V2iV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfacc, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfadd, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfcmpeq, "V2iV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfcmpge, "V2iV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfcmpgt, "V2iV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfmax, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfmin, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfmul, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfrcp, "V2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfrcpit1, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfrcpit2, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfrsqrt, "V2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfrsqit1, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfsub, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pfsubr, "V2fV2fV2f", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pi2fd, "V2fV2i", "ncV:64:", "3dnow")
-TARGET_BUILTIN(__builtin_ia32_pmulhrw, "V4sV4sV4s", "ncV:64:", "3dnow")
-// 3DNow! Extensions (3dnowa).
-TARGET_BUILTIN(__builtin_ia32_pf2iw, "V2iV2f", "ncV:64:", "3dnowa")
-TARGET_BUILTIN(__builtin_ia32_pfnacc, "V2fV2fV2f", "ncV:64:", "3dnowa")
-TARGET_BUILTIN(__builtin_ia32_pfpnacc, "V2fV2fV2f", "ncV:64:", "3dnowa")
-TARGET_BUILTIN(__builtin_ia32_pi2fw, "V2fV2i", "ncV:64:", "3dnowa")
-TARGET_BUILTIN(__builtin_ia32_pswapdsf, "V2fV2f", "ncV:64:", "3dnowa")
-TARGET_BUILTIN(__builtin_ia32_pswapdsi, "V2iV2i", "ncV:64:", "3dnowa")
-
// MMX
//
// All MMX instructions will be generated via builtins. Any MMX vector
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index bbf860aa491e1..78286fecad24f 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6094,10 +6094,6 @@ def mno_80387 : Flag<["-"], "mno-80387">, Alias<mno_x87>;
def mno_fp_ret_in_387 : Flag<["-"], "mno-fp-ret-in-387">, Alias<mno_x87>;
def mmmx : Flag<["-"], "mmmx">, Group<m_x86_Features_Group>;
def mno_mmx : Flag<["-"], "mno-mmx">, Group<m_x86_Features_Group>;
-def m3dnow : Flag<["-"], "m3dnow">, Group<m_x86_Features_Group>;
-def mno_3dnow : Flag<["-"], "mno-3dnow">, Group<m_x86_Features_Group>;
-def m3dnowa : Flag<["-"], "m3dnowa">, Group<m_x86_Features_Group>;
-def mno_3dnowa : Flag<["-"], "mno-3dnowa">, Group<m_x86_Features_Group>;
def mamx_bf16 : Flag<["-"], "mamx-bf16">, Group<m_x86_Features_Group>;
def mno_amx_bf16 : Flag<["-"], "mno-amx-bf16">, Group<m_x86_Features_Group>;
def mamx_complex : Flag<["-"], "mamx-complex">, Group<m_x86_Features_Group>;
@@ -6331,6 +6327,12 @@ def mvevpu : Flag<["-"], "mvevpu">, Group<m_ve_Features_Group>,
def mno_vevpu : Flag<["-"], "mno-vevpu">, Group<m_ve_Features_Group>;
} // let Flags = [TargetSpecific]
+// Unsupported X86 feature flags (triggers a warning)
+def m3dnow : Flag<["-"], "m3dnow">;
+def mno_3dnow : Flag<["-"], "mno-3dnow">;
+def m3dnowa : Flag<["-"], "m3dnowa">;
+def mno_3dnowa : Flag<["-"], "mno-3dnowa">;
+
// These are legacy user-facing driver-level option spellings. They are always
// aliases for options that are spelled using the more common Unix / GNU flag
// style of double-dash and equals-joined flags.
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 036a655a4d073..6083be5ee698e 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -258,7 +258,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
if (Feature[0] != '+')
continue;
- if (Feature == "+aes") {
+ if (Feature == "+mmx") {
+ HasMMX = true;
+ } else if (Feature == "+aes") {
HasAES = true;
} else if (Feature == "+vaes") {
HasVAES = true;
@@ -483,13 +485,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
// for bfloat16 arithmetic operations in the front-end.
HasBFloat16 = SSELevel >= SSE2;
- MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
- .Case("+3dnowa", AMD3DNowAthlon)
- .Case("+3dnow", AMD3DNow)
- .Case("+mmx", MMX)
- .Default(NoMMX3DNow);
- MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
-
XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
.Case("+xop", XOP)
.Case("+fma4", FMA4)
@@ -1025,18 +1020,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
}
// Each case falls through to the previous one here.
- switch (MMX3DNowLevel) {
- case AMD3DNowAthlon:
- Builder.defineMacro("__3dNOW_A__");
- [[fallthrough]];
- case AMD3DNow:
- Builder.defineMacro("__3dNOW__");
- [[fallthrough]];
- case MMX:
+ if (HasMMX) {
Builder.defineMacro("__MMX__");
- [[fallthrough]];
- case NoMMX3DNow:
- break;
}
if (CPU >= CK_i486 || CPU == CK_None) {
@@ -1055,8 +1040,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
return llvm::StringSwitch<bool>(Name)
- .Case("3dnow", true)
- .Case("3dnowa", true)
.Case("adx", true)
.Case("aes", true)
.Case("amx-bf16", true)
@@ -1225,9 +1208,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("widekl", HasWIDEKL)
.Case("lwp", HasLWP)
.Case("lzcnt", HasLZCNT)
- .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
- .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
- .Case("mmx", MMX3DNowLevel >= MMX)
+ .Case("mmx", HasMMX)
.Case("movbe", HasMOVBE)
.Case("movdiri", HasMOVDIRI)
.Case("movdir64b", HasMOVDIR64B)
diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h
index 9b2ae87adb2e7..2ef404dfa18c8 100644
--- a/clang/lib/Basic/Targets/X86.h
+++ b/clang/lib/Basic/Targets/X86.h
@@ -67,12 +67,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
AVX2,
AVX512F
} SSELevel = NoSSE;
- enum MMX3DNowEnum {
- NoMMX3DNow,
- MMX,
- AMD3DNow,
- AMD3DNowAthlon
- } MMX3DNowLevel = NoMMX3DNow;
+ bool HasMMX = false;
enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
enum AddrSpace { ptr32_sptr = 270, ptr32_uptr = 271, ptr64 = 272 };
@@ -346,8 +341,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
return "avx512";
if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
return "avx";
- if (getTriple().getArch() == llvm::Triple::x86 &&
- MMX3DNowLevel == NoMMX3DNow)
+ if (getTriple().getArch() == llvm::Triple::x86 && !HasMMX)
return "no-mmx";
return "";
}
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 931726a78dae9..54fd0de3e20ed 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15936,14 +15936,6 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
return Builder.CreateCall(F, {Ops[0]});
}
- // 3DNow!
- case X86::BI__builtin_ia32_pswapdsf:
- case X86::BI__builtin_ia32_pswapdsi: {
- llvm::Type *MMXTy = llvm::Type::getX86_MMXTy(getLLVMContext());
- Ops[0] = Builder.CreateBitCast(Ops[0], MMXTy, "cast");
- llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_3dnowa_pswapd);
- return Builder.CreateCall(F, Ops, "pswapd");
- }
case X86::BI__builtin_ia32_rdrand16_step:
case X86::BI__builtin_ia32_rdrand32_step:
case X86::BI__builtin_ia32_rdrand64_step:
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index 75f9c99d5d0bf..067d11162cb19 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -312,4 +312,17 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple,
Features.push_back("+prefer-no-scatter");
if (Args.hasArg(options::OPT_mapx_inline_asm_use_gpr32))
Features.push_back("+inline-asm-use-gpr32");
+
+ // Warn for removed 3dnow support
+ if (const Arg *A =
+ Args.getLastArg(options::OPT_m3dnowa, options::OPT_mno_3dnowa,
+ options::OPT_mno_3dnow)) {
+ if (A->getOption().matches(options::OPT_m3dnowa))
+ D.Diag(diag::warn_drv_clang_unsupported) << A->getAsString(Args);
+ }
+ if (const Arg *A =
+ Args.getLastArg(options::OPT_m3dnow, options::OPT_mno_3dnow)) {
+ if (A->getOption().matches(options::OPT_m3dnow))
+ D.Diag(diag::warn_drv_clang_unsupported) << A->getAsString(Args);
+ }
}
diff --git a/clang/lib/Headers/mm3dnow.h b/clang/lib/Headers/mm3dnow.h
index 22ab13aa33409..10049553969f2 100644
--- a/clang/lib/Headers/mm3dnow.h
+++ b/clang/lib/Headers/mm3dnow.h
@@ -7,151 +7,16 @@
*===-----------------------------------------------------------------------===
*/
+// 3dNow intrinsics are no longer supported, and this header remains only as a
+// stub for users who were including it to get to _m_prefetch or
+// _m_prefetchw. Such uses should prefer x86intrin.h.
+
#ifndef _MM3DNOW_H_INCLUDED
#define _MM3DNOW_H_INCLUDED
#include <mmintrin.h>
#include <prfchwintrin.h>
-typedef float __v2sf __attribute__((__vector_size__(8)));
-
-/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("3dnow"), __min_vector_width__(64)))
-
-static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("3dnow")))
-_m_femms(void) {
- __builtin_ia32_femms();
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pavgusb(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pavgusb((__v8qi)__m1, (__v8qi)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pf2id(__m64 __m) {
- return (__m64)__builtin_ia32_pf2id((__v2sf)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfacc(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfacc((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfadd(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfadd((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfcmpeq(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfcmpeq((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfcmpge(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfcmpge((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfcmpgt(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfcmpgt((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfmax(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfmax((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfmin(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfmin((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfmul(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfmul((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfrcp(__m64 __m) {
- return (__m64)__builtin_ia32_pfrcp((__v2sf)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfrcpit1(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfrcpit1((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfrcpit2(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfrcpit2((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfrsqrt(__m64 __m) {
- return (__m64)__builtin_ia32_pfrsqrt((__v2sf)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfrsqrtit1(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfrsqit1((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfsub(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfsub((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfsubr(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfsubr((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pi2fd(__m64 __m) {
- return (__m64)__builtin_ia32_pi2fd((__v2si)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pmulhrw(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pmulhrw((__v4hi)__m1, (__v4hi)__m2);
-}
-
-/* Handle the 3dnowa instructions here. */
-#undef __DEFAULT_FN_ATTRS
-#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("3dnowa"), __min_vector_width__(64)))
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pf2iw(__m64 __m) {
- return (__m64)__builtin_ia32_pf2iw((__v2sf)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfnacc(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfnacc((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pfpnacc(__m64 __m1, __m64 __m2) {
- return (__m64)__builtin_ia32_pfpnacc((__v2sf)__m1, (__v2sf)__m2);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pi2fw(__m64 __m) {
- return (__m64)__builtin_ia32_pi2fw((__v2si)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pswapdsf(__m64 __m) {
- return (__m64)__builtin_ia32_pswapdsf((__v2sf)__m);
-}
-
-static __inline__ __m64 __DEFAULT_FN_ATTRS
-_m_pswapdsi(__m64 __m) {
- return (__m64)__builtin_ia32_pswapdsi((__v2si)__m);
-}
-
#undef __DEFAULT_FN_ATTRS
#endif
diff --git a/clang/lib/Headers/x86intrin.h b/clang/lib/Headers/x86intrin.h
index c20bfbb8fe46e..f42e9e580f883 100644
--- a/clang/lib/Headers/x86intrin.h
+++ b/clang/lib/Headers/x86intrin.h
@@ -14,10 +14,6 @@
#include <immintrin.h>
-#if !defined(__SCE__) || __has_feature(modules) || defined(__3dNOW__)
-#include <mm3dnow.h>
-#endif
-
#if !defined(__SCE__) || __has_feature(modules) || defined(__PRFCHW__)
#include <prfchwintrin.h>
#endif
diff --git a/clang/test/CodeGen/X86/3dnow-builtins.c b/clang/test/CodeGen/X86/3dnow-builtins.c
deleted file mode 100644
index af754b71555c4..0000000000000
--- a/clang/test/CodeGen/X86/3dnow-builtins.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +3dnowa -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=GCC -check-prefix=CHECK
-// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-scei-ps4 -target-feature +3dnowa -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=PS4 -check-prefix=CHECK
-// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-sie-ps5 -target-feature +3dnowa -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=PS4 -check-prefix=CHECK
-
-
-#include <x86intrin.h>
-
-__m64 test_m_pavgusb(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pavgusb
- // GCC-LABEL: define{{.*}} double @test_m_pavgusb
- // CHECK: @llvm.x86.3dnow.pavgusb
- return _m_pavgusb(m1, m2);
-}
-
-__m64 test_m_pf2id(__m64 m) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pf2id
- // GCC-LABEL: define{{.*}} double @test_m_pf2id
- // CHECK: @llvm.x86.3dnow.pf2id
- return _m_pf2id(m);
-}
-
-__m64 test_m_pfacc(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfacc
- // GCC-LABEL: define{{.*}} double @test_m_pfacc
- // CHECK: @llvm.x86.3dnow.pfacc
- return _m_pfacc(m1, m2);
-}
-
-__m64 test_m_pfadd(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfadd
- // GCC-LABEL: define{{.*}} double @test_m_pfadd
- // CHECK: @llvm.x86.3dnow.pfadd
- return _m_pfadd(m1, m2);
-}
-
-__m64 test_m_pfcmpeq(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfcmpeq
- // GCC-LABEL: define{{.*}} double @test_m_pfcmpeq
- // CHECK: @llvm.x86.3dnow.pfcmpeq
- return _m_pfcmpeq(m1, m2);
-}
-
-__m64 test_m_pfcmpge(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfcmpge
- // GCC-LABEL: define{{.*}} double @test_m_pfcmpge
- // CHECK: @llvm.x86.3dnow.pfcmpge
- return _m_pfcmpge(m1, m2);
-}
-
-__m64 test_m_pfcmpgt(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfcmpgt
- // GCC-LABEL: define{{.*}} double @test_m_pfcmpgt
- // CHECK: @llvm.x86.3dnow.pfcmpgt
- return _m_pfcmpgt(m1, m2);
-}
-
-__m64 test_m_pfmax(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfmax
- // GCC-LABEL: define{{.*}} double @test_m_pfmax
- // CHECK: @llvm.x86.3dnow.pfmax
- return _m_pfmax(m1, m2);
-}
-
-__m64 test_m_pfmin(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfmin
- // GCC-LABEL: define{{.*}} double @test_m_pfmin
- // CHECK: @llvm.x86.3dnow.pfmin
- return _m_pfmin(m1, m2);
-}
-
-__m64 test_m_pfmul(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfmul
- // GCC-LABEL: define{{.*}} double @test_m_pfmul
- // CHECK: @llvm.x86.3dnow.pfmul
- return _m_pfmul(m1, m2);
-}
-
-__m64 test_m_pfrcp(__m64 m) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfrcp
- // GCC-LABEL: define{{.*}} double @test_m_pfrcp
- // CHECK: @llvm.x86.3dnow.pfrcp
- return _m_pfrcp(m);
-}
-
-__m64 test_m_pfrcpit1(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfrcpit1
- // GCC-LABEL: define{{.*}} double @test_m_pfrcpit1
- // CHECK: @llvm.x86.3dnow.pfrcpit1
- return _m_pfrcpit1(m1, m2);
-}
-
-__m64 test_m_pfrcpit2(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfrcpit2
- // GCC-LABEL: define{{.*}} double @test_m_pfrcpit2
- // CHECK: @llvm.x86.3dnow.pfrcpit2
- return _m_pfrcpit2(m1, m2);
-}
-
-__m64 test_m_pfrsqrt(__m64 m) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfrsqrt
- // GCC-LABEL: define{{.*}} double @test_m_pfrsqrt
- // CHECK: @llvm.x86.3dnow.pfrsqrt
- return _m_pfrsqrt(m);
-}
-
-__m64 test_m_pfrsqrtit1(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfrsqrtit1
- // GCC-LABEL: define{{.*}} double @test_m_pfrsqrtit1
- // CHECK: @llvm.x86.3dnow.pfrsqit1
- return _m_pfrsqrtit1(m1, m2);
-}
-
-__m64 test_m_pfsub(__m64 m1, __m64 m2) {
- // PS4-LABEL: define{{.*}} i64 @test_m_pfsub
- // GCC-LABEL: define{{.*}} double @test_m_pfsub
- // CHECK: @llvm.x86.3dnow.pfsub
- return _m_pfsub(m1, m2);
-}
-
-__m64 test_m_pfsubr(__m64 m1, __m64 m2) {
- ...
[truncated]
|
phoebewang
reviewed
Jun 21, 2024
|
I'd prefer we rip off ALL the 3dnow/mmx bandaid in one big series of patches - and not split across the 19.X/20.X releases. So can we get all the mmx patches done in time for the 19.0 branch? Also, this "might" have bigger impact than the KNL changes - should we announce the plan in 19.X and do it for 20.X? |
RKSimon
reviewed
Jun 21, 2024
clang/lib/Headers/mm3dnow.h
Outdated
| @@ -7,151 +7,16 @@ | |||
| *===-----------------------------------------------------------------------=== | |||
| */ | |||
|
|
|||
| // 3dNow intrinsics are no longer supported, and this header remains only as a | |||
| // stub for users who were including it to get to _m_prefetch or | |||
| // _m_prefetchw. Such uses should prefer x86intrin.h. | |||
There was a problem hiding this comment.
How best can we add a deprecation warning to builds for people who are doing this?
There was a problem hiding this comment.
Looking at this again, I do think it's reasonable to emit a #warning here.
I was initially worried that might cause issues for users, but there's so very very few users of anything 3dnow-related to start with, and the ones I found generally conditioned the include on __3dNOW__ being defined, anyhow.
llvm/lib/Target/X86/X86.td
Outdated
| @@ -1825,32 +1818,32 @@ def : ProcModel<P, SapphireRapidsModel, | |||
|
|
|||
| def : Proc<"k6", [FeatureX87, FeatureCX8, FeatureMMX], | |||
| [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; | |||
| def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow], | |||
| def : Proc<"k6-2", [FeatureX87, FeatureCX8], | |||
There was a problem hiding this comment.
These still need FeatureMMX and SSEPrefetch (or a similar flag)
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Oops! I had fixed that but in a not-yet-committed diff in my checkout. (Tests fail, otherwise!)
You can test this locally with the following command:git-clang-format --diff 7775be4d48e95385c1968d7f1826a11e08f5f954 a39c9411cd163bd05e0137baced7c63c364bc34f --extensions c,h,cpp -- clang/lib/Basic/Targets/X86.cpp clang/lib/Basic/Targets/X86.h clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Driver/ToolChains/Arch/X86.cpp clang/lib/Headers/mm3dnow.h clang/lib/Headers/x86intrin.h clang/test/CodeGen/builtins-x86.c clang/test/Driver/x86-target-features.c clang/test/Headers/mm3dnow.c clang/test/Preprocessor/predefined-arch-macros.c clang/test/Preprocessor/x86_target_features.c llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86Subtarget.cpp llvm/lib/Target/X86/X86Subtarget.hView the diff from clang-format here.diff --git a/clang/lib/Headers/mm3dnow.h b/clang/lib/Headers/mm3dnow.h
index afffba3a9c..a414fea34c 100644
--- a/clang/lib/Headers/mm3dnow.h
+++ b/clang/lib/Headers/mm3dnow.h
@@ -13,7 +13,8 @@
#define _MM3DNOW_H_INCLUDED
#ifndef _CLANG_DISABLE_CRT_DEPRECATION_WARNINGS
-#warning "The <mm3dnow.h> header is deprecated, and 3dNow! intrinsics are unsupported. For other intrinsics, include <x86intrin.h>, instead."
+#warning \
+ "The <mm3dnow.h> header is deprecated, and 3dNow! intrinsics are unsupported. For other intrinsics, include <x86intrin.h>, instead."
#endif
#include <mmintrin.h>
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index e6fc21ad82..4e8e04b111 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -290,8 +290,7 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
IsUnalignedMem16Slow = false;
LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
- << ", MMX " << HasMMX << ", 64bit "
- << HasX86_64 << "\n");
+ << ", MMX " << HasMMX << ", 64bit " << HasX86_64 << "\n");
if (Is64Bit && !HasX86_64)
report_fatal_error("64-bit code requested on a subtarget that doesn't "
"support it!");
|
RKSimon
reviewed
Jun 21, 2024
llvm/lib/Target/X86/X86.td
Outdated
| @@ -1825,32 +1818,32 @@ def : ProcModel<P, SapphireRapidsModel, | |||
|
|
|||
| def : Proc<"k6", [FeatureX87, FeatureCX8, FeatureMMX], | |||
| [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; | |||
| def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow], | |||
| def : Proc<"k6-2", [FeatureX87, FeatureCX8, FeatureMMX], | |||
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I think the best we can do is add FeaturePRFCHW as well?
The 3dnow part is a lot easier -- because it's not trying to be compatible, just dropping support entirely. And I don't think anyone will care, since 3dnow is effectively never used (even before it was discontinued in 2010, it was barely used). For that same reason -- that it's unused and nobody will notice -- I also think there's not really a reason to wait on removing 3dnow support until other MMX changes are done.
Maybe? Depends on how the discussion on the other PR goes -- whether that proposal is acceptable, or if a different transition strategy is desired. |
|
Was |
|
This LGTM. The prefetch mess was one thing I knew was a little complicated, but it looks like you've taken care of that. |
topperc
reviewed
Jun 25, 2024
Apart from #96540 how many more patches do you envision (still need to remove all the llvm side of things, plus the actual MMX builtins in BuiltinsX86.def - what else?). Should we just put all of that in #96540? |
6 tasks
jyknight
changed the title
|
I've written down an overall plan into issue #98272. I'm not sure if everything can be finished by the LLVM 19 branch date, but I don't think there's any reason to wait on this CL. I'd like to just go ahead with it. |
sayhaan
pushed a commit
to sayhaan/llvm-project
that referenced
this pull request
Jul 16, 2024
Summary: This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. (Clang half originally uploaded in https://reviews.llvm.org/D94213) Works towards issue llvm#41665 and issue llvm#98272. Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D59822396
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I am seeing a lot of while building the Linux kernel (which has |
|
Thanks for the report! Looks like I missed some 3dnow mentions in llvm/lib/TargetParser/X86TargetParser.cpp, so I don't believe it should have any impact other than the warning spam, but I will fix it. |
jyknight
added a commit
to jyknight/llvm-project
that referenced
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Jul 17, 2024
This should've been part of PR llvm#96246, but was missed. This addresses the spurious inclusion of (now unsupported) target features '-3dnow' and '-3dnowa', when disabling mmx.
jyknight
added a commit
that referenced
this pull request
Jul 20, 2024
This addresses the spurious inclusion of (now unsupported) target features '-3dnow' and '-3dnowa' when disabling mmx (when then caused log output from `clang -mno-mmx`). It should've been part of PR #96246, but was missed. Also tweaks the warning in prfchwintrin.h to not recommend the deprecated mm3dnow.h header.
sgundapa
pushed a commit
to sgundapa/upstream_effort
that referenced
this pull request
Jul 23, 2024
This addresses the spurious inclusion of (now unsupported) target features '-3dnow' and '-3dnowa' when disabling mmx (when then caused log output from `clang -mno-mmx`). It should've been part of PR llvm#96246, but was missed. Also tweaks the warning in prfchwintrin.h to not recommend the deprecated mm3dnow.h header.
yuxuanchen1997
pushed a commit
that referenced
this pull request
Jul 25, 2024
This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. (Clang half originally uploaded in https://reviews.llvm.org/D94213) Works towards issue #41665 and issue #98272.
yuxuanchen1997
pushed a commit
that referenced
this pull request
Jul 25, 2024
Summary: This addresses the spurious inclusion of (now unsupported) target features '-3dnow' and '-3dnowa' when disabling mmx (when then caused log output from `clang -mno-mmx`). It should've been part of PR #96246, but was missed. Also tweaks the warning in prfchwintrin.h to not recommend the deprecated mm3dnow.h header. Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251255
github-actions bot
pushed a commit
to smalltalkman/mingw-w64
that referenced
this pull request
Jul 29, 2024
Clang 19 has removed all support for 3dnow, see llvm/llvm-project@f0eb558 and llvm/llvm-project#96246. Since this commit, including the mm3dnow.h header still works, but it produces a warning about the header being deprecated. As 3DNow! has been deprecated for a very long time, stop including this header, for all compiler configurations. This issue was reported in mstorsjo/llvm-mingw#443. Signed-off-by: Martin Storsjö <martin@martin.st>
|
CC @ian-twilightcoder and @vsapsai |
bnbarham
added a commit
to bnbarham/llvm-project
that referenced
this pull request
Aug 30, 2024
Discussing upstream in llvm#96246. For now just remove the warning.
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I think we can just switch it to be a textual header; it no longer has any decls. |
It does still have _MM3DNOW_H_INCLUDED, but we could probably remove that |
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Do the include guard macros make it problematic to expose as a textual header? I would not have thought that to be the case. |
It means that the header guard declaration would be compiled into every pcm that includes the header. Which is maybe fine for this one, but generally isn't good. |
jyknight
added a commit
to jyknight/llvm-project
that referenced
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Sep 3, 2024
This avoids issuing the deprecation diagnostic when building the module. Not building it into a module shouldn't cause any negative impacts, since it no longer has any declarations other than the header guard. It's also very rarely included by anything. Addresses llvm#96246 (comment)
jyknight
added a commit
that referenced
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Sep 13, 2024
This avoids issuing the deprecation diagnostic when building the module. Not building it into a module shouldn't cause any negative impacts, since it no longer has any declarations other than the header guard. It's also very rarely included by anything. Addresses #96246 (comment)
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This set of instructions was only supported by AMD chips starting in
the K6-2 (introduced 1998), and before the "Bulldozer" family
(2011). They were never much used, as they were effectively superseded
by the more-widely-implemented SSE (first implemented on the AMD side
in Athlon XP in 2001).
This is being done as a predecessor towards general removal of MMX
register usage. Since there is almost no usage of the 3DNow!
intrinsics, and no modern hardware even implements them, simple
removal seems like the best option.
(Clang half originally uploaded in https://reviews.llvm.org/D94213)
Works towards issue #41665 and issue #98272.