FMC ADC 250M 16B 4CHA
This project concerns the development of an ADC card in FMC (VITA 57) format. The first intended application is the sampling RF signals in BPM applications, as specified in the BPM project.
- VITA 57.1-2010 compliance
- Four Channel 16 bit 250 MSPS ADC. Required ADC: ISLA216P25
- Internal ADC clock circuit: phase locked to reference clock input
with fine
frequency tuning capability. See specific section. Hold mode in case of loss of
external reference is a desirable feature. - Internal high frequency PLL oscillator output with amplitude control
and locked
to external reference. - Reference clock can be sourced from front panel or from FMC pins
CLK2_BIDIR
and CLK3_BIDIR - The FMC pin CLK_DIR shall be connected to 3P3V via a 10KΩ pull up
resistor to
indicate CLK2_BIDIR and CLK3_BIDIR are driven from the carrier to the FMC
mezzanine. - External ADC clock input (50 MHz up to 250 MHz, 0 dBm typ.)1
- External reference clock input: (0.5 MHz - 20 MHz digital signal, 0 dBm typ.)2
- External digital trigger input
- Documentation:
- Schematics (PDF, Altium sources)
- PCB (PDF, Altium sources)
- Creotech, Poland
| Date | Event |
|---|---|
| 01-09-2012 | Start working on project |
| 01-10-2012 | First version of schematics and PCB component placement |
| 17-11-2012 | Schematic review |
| 19-11-2012 | Schematic bugs fixed, final component placement, added heatsink anad start of PCB routing |
| 23-11-2012 | Board 100% routed. Heat sink design sent to the mechanical workshop for verification. |
| 18-02-2013 | Boards delivered, still waiting for heat sinks and panels |
| 20-05-2013 | Boards fully tested and working. Small issues with S11 caused by baluns and 2V5 supply that is not sufficient for LDOs. With 3V3 works fine |
| 30-09-2014 | v1.1 tested & working |
Filip Świtakowski 04 Feb 2014