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@msaf9
msaf9 committed May 1, 2022
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98 changes: 98 additions & 0 deletions BiDirectionCodeConverterLogisim.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#Base" name="6">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="6" map="Button2" name="Menu Tool"/>
<tool lib="6" map="Button3" name="Menu Tool"/>
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="6" name="Poke Tool"/>
<tool lib="6" name="Edit Tool"/>
<tool lib="6" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin">
<a name="tristate" val="false"/>
</tool>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif plain 12"/>
<wire from="(330,420)" to="(390,420)"/>
<wire from="(330,500)" to="(390,500)"/>
<wire from="(330,320)" to="(390,320)"/>
<wire from="(390,420)" to="(420,420)"/>
<wire from="(390,460)" to="(420,460)"/>
<wire from="(480,440)" to="(510,440)"/>
<wire from="(490,340)" to="(510,340)"/>
<wire from="(490,240)" to="(510,240)"/>
<wire from="(390,460)" to="(390,500)"/>
<wire from="(390,500)" to="(510,500)"/>
<wire from="(330,220)" to="(430,220)"/>
<wire from="(390,360)" to="(390,420)"/>
<wire from="(390,260)" to="(390,320)"/>
<wire from="(390,360)" to="(430,360)"/>
<wire from="(390,320)" to="(430,320)"/>
<wire from="(390,260)" to="(430,260)"/>
<comp lib="1" loc="(480,440)" name="XOR Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="5" loc="(510,500)" name="LED"/>
<comp lib="0" loc="(330,320)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="0" loc="(330,420)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="5" loc="(510,240)" name="LED"/>
<comp lib="1" loc="(490,240)" name="XOR Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="5" loc="(510,340)" name="LED"/>
<comp lib="1" loc="(490,340)" name="XOR Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="5" loc="(510,440)" name="LED"/>
<comp lib="0" loc="(330,500)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="0" loc="(330,220)" name="Pin">
<a name="tristate" val="false"/>
</comp>
</circuit>
</project>
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183 changes: 183 additions & 0 deletions UsingAndNotOrGates.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1">
<tool name="OR Gate">
<a name="inputs" val="2"/>
</tool>
</lib>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#Base" name="6">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="6" map="Button2" name="Menu Tool"/>
<tool lib="6" map="Button3" name="Menu Tool"/>
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="6" name="Poke Tool"/>
<tool lib="6" name="Edit Tool"/>
<tool lib="6" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin">
<a name="tristate" val="false"/>
</tool>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif plain 12"/>
<wire from="(500,140)" to="(550,140)"/>
<wire from="(500,320)" to="(550,320)"/>
<wire from="(240,580)" to="(360,580)"/>
<wire from="(210,250)" to="(260,250)"/>
<wire from="(240,480)" to="(290,480)"/>
<wire from="(240,620)" to="(550,620)"/>
<wire from="(210,110)" to="(210,250)"/>
<wire from="(210,290)" to="(210,440)"/>
<wire from="(420,160)" to="(420,190)"/>
<wire from="(420,340)" to="(420,370)"/>
<wire from="(260,440)" to="(360,440)"/>
<wire from="(420,460)" to="(420,490)"/>
<wire from="(170,440)" to="(210,440)"/>
<wire from="(320,110)" to="(360,110)"/>
<wire from="(320,170)" to="(360,170)"/>
<wire from="(320,290)" to="(360,290)"/>
<wire from="(320,350)" to="(360,350)"/>
<wire from="(260,250)" to="(260,350)"/>
<wire from="(210,110)" to="(240,110)"/>
<wire from="(210,290)" to="(240,290)"/>
<wire from="(420,120)" to="(450,120)"/>
<wire from="(420,160)" to="(450,160)"/>
<wire from="(420,300)" to="(450,300)"/>
<wire from="(420,340)" to="(450,340)"/>
<wire from="(260,540)" to="(290,540)"/>
<wire from="(260,70)" to="(260,170)"/>
<wire from="(240,110)" to="(240,210)"/>
<wire from="(240,290)" to="(240,390)"/>
<wire from="(240,580)" to="(240,620)"/>
<wire from="(410,90)" to="(420,90)"/>
<wire from="(410,190)" to="(420,190)"/>
<wire from="(410,270)" to="(420,270)"/>
<wire from="(410,370)" to="(420,370)"/>
<wire from="(170,480)" to="(240,480)"/>
<wire from="(500,510)" to="(550,510)"/>
<wire from="(240,210)" to="(360,210)"/>
<wire from="(240,390)" to="(360,390)"/>
<wire from="(240,110)" to="(290,110)"/>
<wire from="(240,290)" to="(290,290)"/>
<wire from="(210,440)" to="(260,440)"/>
<wire from="(420,90)" to="(420,120)"/>
<wire from="(260,70)" to="(360,70)"/>
<wire from="(260,250)" to="(360,250)"/>
<wire from="(420,270)" to="(420,300)"/>
<wire from="(420,530)" to="(420,560)"/>
<wire from="(170,250)" to="(210,250)"/>
<wire from="(320,480)" to="(360,480)"/>
<wire from="(320,540)" to="(360,540)"/>
<wire from="(260,440)" to="(260,540)"/>
<wire from="(420,490)" to="(450,490)"/>
<wire from="(420,530)" to="(450,530)"/>
<wire from="(170,70)" to="(260,70)"/>
<wire from="(260,170)" to="(290,170)"/>
<wire from="(260,350)" to="(290,350)"/>
<wire from="(240,480)" to="(240,580)"/>
<wire from="(410,460)" to="(420,460)"/>
<wire from="(410,560)" to="(420,560)"/>
<comp lib="1" loc="(410,190)" name="AND Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="1" loc="(410,90)" name="AND Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="1" loc="(320,350)" name="NOT Gate"/>
<comp lib="1" loc="(320,110)" name="NOT Gate"/>
<comp lib="1" loc="(320,170)" name="NOT Gate"/>
<comp lib="1" loc="(500,140)" name="OR Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="1" loc="(500,510)" name="OR Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="1" loc="(410,560)" name="AND Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="1" loc="(410,370)" name="AND Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="0" loc="(550,620)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="0" loc="(170,480)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="1" loc="(410,270)" name="AND Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="1" loc="(320,480)" name="NOT Gate"/>
<comp lib="0" loc="(170,440)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="0" loc="(550,140)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="1" loc="(320,290)" name="NOT Gate"/>
<comp lib="1" loc="(410,460)" name="AND Gate">
<a name="inputs" val="2"/>
</comp>
<comp lib="0" loc="(170,250)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="0" loc="(170,70)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="1" loc="(320,540)" name="NOT Gate"/>
<comp lib="0" loc="(550,510)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="0" loc="(550,320)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="1" loc="(500,320)" name="OR Gate">
<a name="inputs" val="2"/>
</comp>
</circuit>
</project>
Binary file added UsingAndNotOrGates.png
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