SM83: Zero upper address lines after each mem cyc

msinger · Feb 21, 2021 · b3a7b45 · b3a7b45
1 parent ee47ddb
commit b3a7b45
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Showing 2 changed files with 37 additions and 9 deletions.
diff --git a/src/cpu/sm83_control.sv b/src/cpu/sm83_control.sv
@@ -1554,8 +1554,13 @@ module sm83_control(
 					m2 && t2,
 					m2 && t3:;
 
-					/* Read register F into ALU flags */
-					m2 && t4: af_to_alu(Z|N|H|C);
+					m2 && t4: begin
+						/* Read register F into ALU flags */
+						af_to_alu(Z|N|H|C);
+
+						/* Apply address latch to address bus for write cycle */
+						ctl_io_adr_we        = 1; /* posedge */
+					end
 
 					m3 && t1: begin
 						/* Write data latch into ALU operand A */
@@ -2050,8 +2055,13 @@ module sm83_control(
 					m2 && t2,
 					m2 && t3:;
 
-					/* Read register F into ALU flags */
-					m2 && t4: af_to_alu(Z|N|H|C);
+					m2 && t4: begin
+						/* Read register F into ALU flags */
+						af_to_alu(Z|N|H|C);
+
+						/* Apply address latch to address bus for write cycle */
+						ctl_io_adr_we        = 1; /* posedge */
+					end
 
 					m3 && t1: begin
 						/* Write data latch into ALU operands with shift */
@@ -2163,8 +2173,13 @@ module sm83_control(
 					m2 && t2,
 					m2 && t3:;
 
-					/* Read register F into ALU flags */
-					m2 && t4: af_to_alu(Z|N|H|C);
+					m2 && t4: begin
+						/* Read register F into ALU flags */
+						af_to_alu(Z|N|H|C);
+
+						/* Apply address latch to address bus for write cycle */
+						ctl_io_adr_we        = 1; /* posedge */
+					end
 
 					m3 && t1: begin
 						/* Write data latch into ALU operand B */
@@ -2397,7 +2412,10 @@ module sm83_control(
 						dl_to_alu_bsel();
 					end
 
-					m2 && t4:;
+					m2 && t4: begin
+						/* Apply address latch to address bus for write cycle */
+						ctl_io_adr_we        = 1; /* posedge */
+					end
 
 					m3 && t1: begin
 						/* Write data latch into ALU operand A */
@@ -2500,7 +2518,10 @@ module sm83_control(
 						dl_to_alu_bsel();
 					end
 
-					m2 && t4:;
+					m2 && t4: begin
+						/* Apply address latch to address bus for write cycle */
+						ctl_io_adr_we        = 1; /* posedge */
+					end
 
 					m3 && t1: begin
 						/* Write data latch into ALU operand A */

diff --git a/src/cpu/sm83_io.sv b/src/cpu/sm83_io.sv
@@ -81,7 +81,14 @@ module sm83_io
 		endcase
 	end
 
-	always_ff @(posedge clk) if (al_we) aout = ain;
+	always_ff @(posedge clk) begin
+		/* Zero upper address lines after each memory cycle */
+		if (t4)
+			aout[ADR_WIDTH-1:8] = 0;
+
+		if (al_we)
+			aout = ain;
+	end
 
 	/* Emulate latch behaviour for data input.
 	 * Input data is already latched at IO port, but only for one tick (during T4). */