The HPDcache is an open-source High-Performance, Multi-requester, Out-of-Order L1 Dcache for RISC-V cores and accelerators.
| Directory | Description |
|---|---|
| rtl | Contains the file lists to be used for the compiling of the HPDcache |
| rtl/src | Contains the SystemVerilog RTL sources of the HPDcache |
| rtl/src/target | Contains processor-dependent sources (e.g. adapter modules for the CVA6 core) |
| docs | Contains documentation of the HPDcache |
The HPDcache specification document can be found in the docs/hpdcache_spec_document folder. It is written in LaTeX. You cand find pre-compiled PDF documents in docs/hpdcache_spec_document/release.
If you need to recompile the specification document, a dedicated Makefile is in the specification folder. This Makefile needs the latexmk command-line tool (included in most common LaTeX distributions) and the inkscape tool to convert SVG images into PDF.
The HPDcache is released under the Solderpad Hardware License (version 2.1). Please refer to the LICENSE file for further information.
The HPDcache is integrated with the CVA6 core.
The HPDcache repository (this repository) is included as a submodule of the CVA6 Git.
After you clone the CVA6 repository, be sure to pass the config_pkg::HPDCACHE value to the DCacheType parameter.
This selects the HPDcache as the L1 Data Cache of the core.
For example, the CVA6 configuration package cv64a6_imafdc_sv39_hpdcache_config_pkg.sv does this.
The HPDcache is instantiated in the cva6_hpdcache_subsystem.sv file. You may take a look if you want to integrate the HPDcache with another core.
You may look into the docs/lint subdirectory of this repository to see an integration example of the HPDcache (hpdcache_lint.sv).
This example uses the macros defined in the hpdcache_typedef.svh file. These macros ease the definition of types required by the interface of the HPDcache module.
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Technical Paper: César Fuguet. 2023. HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores. In Proceedings of the 20th ACM International Conference on Computing Frontiers (CF '23). Association for Computing Machinery, New York, NY, USA, 377–378. https://doi.org/10.1145/3587135.3591413
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Video: César Fuguet. 2023. High Performance L1 Dcache for RISC-V Cores. TRISTAN Workshop. RISC-V Summit Europe 2023. https://www.youtube.com/watch?v=3r5STMiUq9s
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Video: Christian Fabre, César Fuguet. 2023. One Year of Improvements on OpenHW Group's HPDCache. RISC-V Summit US 2023. https://www.youtube.com/watch?v=ODHA-wPOmW0