trivial: update rust, deps, fix lints

Update Rust and dependencies and fix uncovered lints.

Signed-off-by: Dan Cross <cross@oxidecomputer.com>

rust-toolchain

@@ -1,3 +1,3 @@
 [toolchain]
-channel = "nightly-2024-03-19"
+channel = "nightly-2024-09-04"
 components = [ "rustfmt", "rust-src", "llvm-tools", "clippy", "miri" ]

src/loader.rs

@@ -35,7 +35,7 @@ pub(crate) fn load(
         }
         load_segment(page_table, section, &bytes[file_range])?;
     }
-    Ok(unsafe { core::mem::transmute::<_, Thunk>(elf.entry) })
+    Ok(unsafe { core::mem::transmute::<u64, Thunk>(elf.entry) })
 }
 
 /// Parses the ELF executable contained in the given byte slice.

src/main.rs

@@ -2,11 +2,10 @@
 // License, v. 2.0. If a copy of the MPL was not distributed with this
 // file, You can obtain one at https://mozilla.org/MPL/2.0/.
 
-#![feature(allocator_api, new_uninit)]
-#![feature(asm_const)]
+#![feature(allocator_api)]
 #![feature(exposed_provenance)]
 #![feature(naked_functions)]
-#![feature(pointer_is_aligned)]
+#![feature(pointer_is_aligned_to)]
 #![feature(strict_provenance)]
 #![feature(sync_unsafe_cell)]
 #![cfg_attr(not(any(test, clippy)), no_std)]
@@ -51,9 +50,9 @@ fn expand_ramdisk() -> &'static [u8] {
     use miniz_oxide::inflate::core::DecompressorOxide;
     use miniz_oxide::inflate::TINFLStatus;
 
-    #[cfg(all(target_vendor = "oxide", target_os = "none"))]
+    #[cfg(target_os = "none")]
     let cpio = include_bytes!(env!("PHBL_PHASE1_COMPRESSED_CPIO_ARCHIVE_PATH"));
-    #[cfg(not(all(target_vendor = "oxide", target_os = "none")))]
+    #[cfg(not(target_os = "none"))]
     let cpio = [0u8; 1];
 
     let dst = phbl::ramdisk_region_init_mut();

src/mmu.rs

@@ -920,7 +920,7 @@ impl PageTable {
         if !self.is_mapped(va) {
             return Err(Error::BadPointer);
         }
-        let ptr = core::ptr::from_exposed_addr_mut::<()>(va);
+        let ptr = core::ptr::with_exposed_provenance_mut::<()>(va);
         if !ptr.is_aligned_to(core::mem::align_of::<T>()) {
             return Err(Error::BadPointer);
         }

src/uart.rs

@@ -443,7 +443,7 @@ impl Device {
     }
 
     fn reset<'a>(self) -> &'a mut ConfigMmio {
-        let regs = core::ptr::from_exposed_addr_mut::<ConfigMmio>(self.addr());
+        let regs = ptr::with_exposed_provenance_mut::<ConfigMmio>(self.addr());
         let uart = unsafe { &mut *regs };
         unsafe {
             ptr::write_volatile(
@@ -472,7 +472,7 @@ impl Uart {
     }
 
     fn write_mmio_mut(&mut self) -> &mut MmioWrite {
-        let regs = core::ptr::from_exposed_addr_mut::<MmioWrite>(self.0.addr());
+        let regs = ptr::with_exposed_provenance_mut::<MmioWrite>(self.0.addr());
         unsafe { &mut *regs }
     }
 
@@ -481,7 +481,7 @@ impl Uart {
     // it is mutually exclusive with a write MMIO structure,
     // as the two share the same register space.
     fn read_mmio_mut(&mut self) -> &mut MmioRead {
-        let regs = core::ptr::from_exposed_addr_mut::<MmioRead>(self.0.addr());
+        let regs = ptr::with_exposed_provenance_mut::<MmioRead>(self.0.addr());
         unsafe { &mut *regs }
     }
 

x86_64-oxide-none-elf.json

@@ -13,7 +13,7 @@
 	"code-model": "small",
 	"frame-pointer": "always",
 	"disable-redzone": true,
-	"features": "-3dnow,-3dnowa,-avx,-avx2,-avx512bf16,-f16c,-fxsr,-mmx,-sse,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-x87,-soft-float",
+	"features": "-avx,-avx2,-avx512bf16,-f16c,-fxsr,-mmx,-sse,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-x87,-soft-float",
 	"linker-flavor": "ld",
 	"linker": "gld",
 	"no-default-libraries": "true",