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Data acquisition of multiple AXI-S streams to a memory connected via AXI-MM (e.g. DDR memory) written in VHDL

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paulscherrerinstitute/psi_multi_stream_daq

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General Information

Maintainer

Daniele Felici [daniele.felici@psi.ch]

Author

Oliver Bründler [oli.bruendler@gmx.ch]

License

This library is published under PSI HDL Library License, which is LGPL plus some additional exceptions to clarify the LGPL terms in the context of firmware development.

Detailed Documentation

Tagging Policy

Stable releases are tagged in the form major.minor.bugfix.

  • Whenever a change is not fully backward compatible, the major version number is incremented
  • Whenever new features are added, the minor version number is incremented
  • If only bugs are fixed (i.e. no functional changes are applied), the bugfix version is incremented

Changelog

See Changelog

Dependencies

The required folder structure looks as given below (folder names must be matched exactly).

Alternatively the repository psi_fpga_all can be used. This repo contains all FPGA related repositories as submodules in the correct folder structure.

Dependencies can also be checked out using the python script scripts/dependencies.py. For details, refer to the help of the script:

python dependencies.py -help

Note that the dependencies package must be installed in order to run the script.

Simulations and Testbenches

A regression test script for Modelsim is present. To run the regression test, execute the following command in modelsim from within the directory sim

source ./run.tcl

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Data acquisition of multiple AXI-S streams to a memory connected via AXI-MM (e.g. DDR memory) written in VHDL

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