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platform: msm8916: clock: Add missing I2C QUP1, QUP3 and QUP6
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This allows using them from LK if needed.
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@stephan-gh
stephan-gh committed Feb 21, 2022
1 parent bceb73b commit 7e9eafe
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Showing 2 changed files with 96 additions and 0 deletions.
13 changes: 13 additions & 0 deletions platform/msm8916/include/platform/iomap.h
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Original file line number Diff line number Diff line change
Expand Up @@ -108,10 +108,19 @@

/* I2C */
#define BLSP_QUP_BASE(blsp_id, qup_id) (PERIPH_SS_BASE + 0xB5000 + 0x1000 * qup_id)

#define GCC_BLSP1_QUP1_APPS_CBCR (CLK_CTL_BASE + 0x2008)
#define GCC_BLSP1_QUP1_CFG_RCGR (CLK_CTL_BASE + 0x2010)
#define GCC_BLSP1_QUP1_CMD_RCGR (CLK_CTL_BASE + 0x200C)

#define GCC_BLSP1_QUP2_APPS_CBCR (CLK_CTL_BASE + 0x3010)
#define GCC_BLSP1_QUP2_CFG_RCGR (CLK_CTL_BASE + 0x3004)
#define GCC_BLSP1_QUP2_CMD_RCGR (CLK_CTL_BASE + 0x3000)

#define GCC_BLSP1_QUP3_APPS_CBCR (CLK_CTL_BASE + 0x4020)
#define GCC_BLSP1_QUP3_CFG_RCGR (CLK_CTL_BASE + 0x4004)
#define GCC_BLSP1_QUP3_CMD_RCGR (CLK_CTL_BASE + 0x4000)

#define GCC_BLSP1_QUP4_APPS_CBCR (CLK_CTL_BASE + 0x5020)
#define GCC_BLSP1_QUP4_CFG_RCGR (CLK_CTL_BASE + 0x5004)
#define GCC_BLSP1_QUP4_CMD_RCGR (CLK_CTL_BASE + 0x5000)
Expand All @@ -120,6 +129,10 @@
#define GCC_BLSP1_QUP5_CFG_RCGR (CLK_CTL_BASE + 0x6004)
#define GCC_BLSP1_QUP5_CMD_RCGR (CLK_CTL_BASE + 0x6000)

#define GCC_BLSP1_QUP6_APPS_CBCR (CLK_CTL_BASE + 0x7020)
#define GCC_BLSP1_QUP6_CFG_RCGR (CLK_CTL_BASE + 0x7004)
#define GCC_BLSP1_QUP6_CMD_RCGR (CLK_CTL_BASE + 0x7000)

/* GPLL */
#define GPLL0_STATUS (CLK_CTL_BASE + 0x2101C)
#define GPLL1_STATUS (CLK_CTL_BASE + 0x2001C)
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83 changes: 83 additions & 0 deletions platform/msm8916/msm8916-clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -567,6 +567,29 @@ static struct vote_clk gcc_ce1_axi_clk = {
},
};

static struct rcg_clk gcc_blsp1_qup1_i2c_apps_clk_src =
{
.cmd_reg = (uint32_t *) GCC_BLSP1_QUP1_CMD_RCGR,
.cfg_reg = (uint32_t *) GCC_BLSP1_QUP1_CFG_RCGR,
.set_rate = clock_lib2_rcg_set_rate_hid,
.freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,

.c = {
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
},
};

static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
.cbcr_reg = (uint32_t *) GCC_BLSP1_QUP1_APPS_CBCR,
.parent = &gcc_blsp1_qup1_i2c_apps_clk_src.c,

.c = {
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
},
};

static struct rcg_clk gcc_blsp1_qup2_i2c_apps_clk_src =
{
Expand All @@ -592,6 +615,30 @@ static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
},
};

static struct rcg_clk gcc_blsp1_qup3_i2c_apps_clk_src =
{
.cmd_reg = (uint32_t *) GCC_BLSP1_QUP3_CMD_RCGR,
.cfg_reg = (uint32_t *) GCC_BLSP1_QUP3_CFG_RCGR,
.set_rate = clock_lib2_rcg_set_rate_hid,
.freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,

.c = {
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
},
};

static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
.cbcr_reg = (uint32_t *) GCC_BLSP1_QUP3_APPS_CBCR,
.parent = &gcc_blsp1_qup3_i2c_apps_clk_src.c,

.c = {
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
},
};

static struct rcg_clk gcc_blsp1_qup4_i2c_apps_clk_src =
{
.cmd_reg = (uint32_t *) GCC_BLSP1_QUP4_CMD_RCGR,
Expand Down Expand Up @@ -640,6 +687,30 @@ static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
},
};

static struct rcg_clk gcc_blsp1_qup6_i2c_apps_clk_src =
{
.cmd_reg = (uint32_t *) GCC_BLSP1_QUP6_CMD_RCGR,
.cfg_reg = (uint32_t *) GCC_BLSP1_QUP6_CFG_RCGR,
.set_rate = clock_lib2_rcg_set_rate_hid,
.freq_tbl = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
.current_freq = &rcg_dummy_freq,

.c = {
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk_src",
.ops = &clk_ops_rcg,
},
};

static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
.cbcr_reg = (uint32_t *) GCC_BLSP1_QUP6_APPS_CBCR,
.parent = &gcc_blsp1_qup6_i2c_apps_clk_src.c,

.c = {
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
},
};

/* Clock lookup table */
static struct clk_lookup msm_clocks_8916[] =
{
Expand Down Expand Up @@ -671,17 +742,29 @@ static struct clk_lookup msm_clocks_8916[] =
CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c),

CLK_LOOKUP("blsp1_qup1_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk_src", gcc_blsp1_qup1_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup1_i2c_apps_clk", gcc_blsp1_qup1_i2c_apps_clk.c),

CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c),

CLK_LOOKUP("blsp1_qup3_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk_src", gcc_blsp1_qup3_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup3_i2c_apps_clk", gcc_blsp1_qup3_i2c_apps_clk.c),

CLK_LOOKUP("blsp1_qup4_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk_src", gcc_blsp1_qup4_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk", gcc_blsp1_qup4_i2c_apps_clk.c),

CLK_LOOKUP("blsp1_qup5_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk_src", gcc_blsp1_qup5_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup5_i2c_apps_clk", gcc_blsp1_qup5_i2c_apps_clk.c),

CLK_LOOKUP("blsp1_qup6_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk_src", gcc_blsp1_qup6_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp1_qup6_i2c_apps_clk", gcc_blsp1_qup6_i2c_apps_clk.c),
};

#define APCS_ALIAS0_CMD_RCGR_BASE 0xb111050
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