Remove verilog compile

phanrahan · Mar 22, 2024 · 8c4886f · 8c4886f
1 parent 687865d
commit 8c4886f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/tests/test_syntax/test_fsm.py b/tests/test_syntax/test_fsm.py
@@ -50,5 +50,5 @@ class Foo(m.Circuit):
                     io.O @= i
                     state.next @= states[(i + 1) % 3]
 
-    m.compile("build/test_fsm_loop_unroll", Foo, output="mlir-verilog")
+    m.compile("build/test_fsm_loop_unroll", Foo, output="mlir")
     assert check_gold(__file__, "test_fsm_loop_unroll.mlir")