Add ghidra decompile result

[Yangff]

Please notice that currently ghidra's riscv plugin does not support floating

[Yangff]

will merge again after add memory maps

[WildCryptoFox]

@Yangff you can set the PR as a draft; then push new commits (or amend the previous commit).

[mumbel]

Please notice that currently ghidra's riscv plugin does not support floating

How so, because it most certainly has FP support? I am only aware that there were 2 broken FP instructions, c.fsw and c.fswsp, before you made this PR, can you open an issue on my repo with what you're seeing.

[Yangff]

Please notice that currently ghidra's riscv plugin does not support floating

How so, because it most certainly has FP support? I am only aware that there were 2 broken FP instructions, c.fsw and c.fswsp, before you made this PR, can you open an issue on my repo with what you're seeing.

hmmm.. can you see what's in rfc_init function?

                             *************************************************************
                             *                           FUNCTION                          
                             *************************************************************
                             void  __stdcall  rfc_init (uint32_t  xtalfreq_hz )
             void              <VOID>         <RETURN>
             uint32_t          a0:4           xtalfreq_hz
             uint32_t          Stack[-0x50]:4 dg
             uint32_t          Stack[-0x54]:4 rfg_index
                             rfc_init                                        XREF[2]:     Entry Point (*) , 
                                                                                          wifi_main:230133bc (c)   
        2301503e 1d  71           c.addi16   sp,-0x60
        23015040 a6  ca           c.swsp     s1,0x54 (sp)
        23015042 86  ce           c.swsp     ra,0x5c (sp)
        23015044 a2  cc           c.swsp     s0,0x58 (sp)
        23015046 ca  c8           c.swsp     s2,0x50 (sp)
        23015048 ce  c6           c.swsp     s3,0x4c (sp)
        2301504a d2  c4           c.swsp     s4,0x48 (sp)
        2301504c d6  c2           c.swsp     s5,0x44 (sp)
        2301504e da  c0           c.swsp     s6,0x40 (sp)
        23015050 5e  de           c.swsp     s7,0x3c (sp)
        23015052 62  dc           c.swsp     s8,0x38 (sp)
        23015054 66  da           c.swsp     s9,0x34 (sp)
        23015056 6a  d8           c.swsp     s10 ,0x30 (sp)
        23015058 6e  d6           c.swsp     s11 ,0x2c (sp)
        2301505a 22              ??         22h    "
        2301505b ee              ??         EEh
        2301505c 26              ??         26h    &
        2301505d ec              ??         ECh
        2301505e 37              ??         37h    7

[stschake]

@Yangff this is fixed in the latest version of the RISCV plugin and the instruction starting at 2301505a correctly disassembled as c.fswsp

[mumbel]

@stschake beat me to it, sorry should have been more specific, I had just fixed that when I posted in the other thread, and you would have needed to update. That will decode now into fsw instructions