import other DWARF info and done

pine64 · Yangff · Jul 21, 2021 · Jul 21, 2021 · Jul 21, 2021 · Jul 21, 2021
commit 80069a967bf92bc6e1bfc4db1307371a29c4b985
diff --git a/script/manualext.py b/script/manualext.py
@@ -12,33 +12,33 @@
 Field('txcbwmax', 0xfcffffff) # Channel bandwidth
 Field('txnssmax', 0xffffff8f) # number of spatial streams
 Field('ntxmax', 0xff8fffff) # tx chan?
-Field('v18', 0xfffffeff) # some switch? DAT_44c00000>>18
+Field('txldpcen', 0xfffffeff) # some switch? DAT_44c00000>>18
 Field('vht', 0xfffffffd) # very high throughput
-Field('v31', 0xfffeffff) # some switch? DAT_44c00000>>31
+Field('txmumimoen', 0xfffeffff) # some switch? DAT_44c00000>>31
 
 Reg('rxchan', 0x44c00820)
 Field('rxcbwmax', 0xfcffffff) # Channel bandwidth
 Field('rxnssmax', 0xffffff8f) # number of spatial streams
 # Field('nrxmax', 0xff8fffff) # not exists
-Field('v19', 0xfffffeff) # some switch? DAT_44c00000>>19
-Field('vht', 0xfffffffd) # very high throughput
-Field('v30', 0xfffeffff) # some switch? DAT_44c00000>>30
-Field('_v30', 0xffefffff) # some switch? DAT_44c00000>>30
-FieldBit('reset', 0) # set 1 in phy_hw_set_channel for.. reset?
+Field('rxldpcen', 0xfffffeff) # some switch? DAT_44c00000>>19
+Field('rxvhten', 0xfffffffd) # very high throughput
+Field('rxmumimoen', 0xfffeffff) # some switch? DAT_44c00000>>30
+Field('rxmumimoapeplenen', 0xffefffff) # some switch? DAT_44c00000>>30
+FieldBit('rxdsssen', 0) # set 1 in phy_hw_set_channel for.. reset?
 Field('rxndpnstsmax', 0xffff8fff)
 
 Reg('version', 0x44c00000)
 FieldBit('vht', 31-9)
 FieldBit('nss', 8, 4) # phy_get_nss (nss + 1)
-FieldBit('rxndpnstsmax', 0xc, 4)
-FieldBit('v18', 0x12)
-FieldBit('v19', 0x13)
+FieldBit('nsts', 0xc, 4)
+FieldBit('ldpcenc', 0x12)
+FieldBit('ldpcdec', 0x13)
 FieldBit('mu_mimo_rx', 0x1e)
 FieldBit('mu_mimo_tx', 0x1f)
 FieldBit('ldpctx', 0x1a)
 FieldBit('ldpcrx', 0x1b)
 FieldBit('ntx', 4, 4) # phy_get_ntx (ntx + 1)
-FieldBit('txcbwmax', 0x18, 2)
+FieldBit('chbw', 0x18, 2)
 FieldBit('bfmee_supported', 0x1c)
 FieldBit('bfmer_supported', 0x1d)
 
@@ -50,9 +50,9 @@
 FieldBit('FSMSWRESET', 4)
 FieldBit('MDMSWRESET', 0)
 
-Reg('TXCTRL0', 0x44c00838)
-Reg('TXCTRL1', 0x44c0088c)
-Reg('TXCTRL3', 0x44c00898)
+Reg('txstartdelay', 0x44c00838)
+Reg('txctrl1', 0x44c0088c)
+Reg('txctrl3', 0x44c00898)
 
 Reg('TBECTRL0', 0x44c00858)
 Field('tbe_count_adjust_20', 0xffffff00)
@@ -62,8 +62,8 @@
 Field('WAITHTSTF', 0xffffff80)
 
 Reg('r834', 0x44c00834)
-Field('set60h', 0x00ffffff)
-FieldBit('set1', 0)
+Field('tddchtstfmargin', 0x00ffffff)
+FieldBit('rxtdctrl1', 0)
 
 Reg('SMOOTHCTRL', 0x44c00818)
 FieldBit('TDCYCROTVAL20', 0, 8)
@@ -93,7 +93,7 @@
 Reg('rxctrl1', 0x44c0083c) # reset to 0x4920492
 
 Reg('r0x874', 0x44c00874)
-Field('resetto1', 0xf7ffffff)
+Field('rcclkforce', 0xf7ffffff)
 Field('mdm_agcmemclkforce', 0xdfffffff)
 #print('\n'.join(GenSVD()))
 
@@ -116,9 +116,9 @@
 
 
 Reg('RWNXAGCCNTL', 0x44c0b390)
-Field('set1', 0xfffffffc)
+Field('combpathsel', 0xfffffffc)
 Field('agcfsmreset', 0xffffefff) # set 1 before agc mem, maybe
-
+Field('rifsdeten', 0xfffffbff)
 Reg('riu_rwnxagcaci20marg0', 0x44c0b340)
 Reg('riu_rwnxagcaci20marg1', 0x44c0b344)
 Reg('riu_rwnxagcaci20marg2', 0x44c0b348)
@@ -132,13 +132,14 @@
 Reg('irqmacccatimeouten', 0x44c0b414)
 Field('set1', 0xFFFFFEFF)
 
-Reg('r41c', 0x44c0b41c)
+Reg('rwnxmacintstatmasked', 0x44c0b41c)
 FieldBit('needreset', 8) # guess
-Reg('r420_copy41c', 0x44c0b420)
+
+Reg('rwnxmacintack', 0x44c0b420)
 
 
 Reg('rc218', 0x44c0c218)
-Field('set0', 0xffff0000)
+Field('txhbf20coeffsel', 0xffff0000)
 
 Buf('rxgain_offset_vs_temperature', 0x44c0c080, 0x44c0c088, 1)
 
@@ -347,13 +348,13 @@ def getregs(fname, pattern='name'):
 
 peris['dma'] = Peripheral(peripheral('dma', 0x44a00000, 0x1000))
 
-Reg('status', 0x44a00024)
+Reg('int_status', 0x44a00024)
 Field("TX", 0x1f)
 FieldBit("RXHeader", 5) ## guess
 FieldBit("RXPayload", 6) ## guess
 FieldBit("b8", 8)
 
-Reg('tx_reset', 0x44a00020) # my guess, setting of r20 should reset 0x24??
+Reg('int_ack', 0x44a00020) # my guess, setting of r20 should reset 0x24??
 # kind like response...
 FieldBit("b8", 8) # set at txl_cfm_dma_int_handler
 FieldBit("b7", 7) # set at ipc_emb_dbg_dma_int_handler
@@ -362,9 +363,10 @@ def getregs(fname, pattern='name'):
 Field("TX", 0x1f)
 
 Reg("dma_status", 0x44a00010)
-Field("busyatffff", 0xffff)
+Field("dma_status_oft_free", 0xffff)
 
 # my guess!!
+# access with dma_lli_counter_get(reg_idx)
 Reg('TX_BCN', 0x44a00080)
 FieldBit('bridgedmacnt', 0, 16)
 Reg('TX_AC_0', 0x44a00084)
@@ -377,9 +379,9 @@ def getregs(fname, pattern='name'):
 FieldBit('bridgedmacnt', 0, 16)
 
 Reg('LinkListItem0', 0x44a000a4)
-FieldBit("lli", 0, 16)
+FieldBit("counter", 0, 16)
 Reg('LinkListItem1', 0x44a000ac)
-FieldBit("lli", 0, 16)
+FieldBit("counter", 0, 16)
 
 #open('../src/include/phy/dma.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
@@ -390,16 +392,14 @@ def getregs(fname, pattern='name'):
 peris['sysctrl'] = Peripheral(peripheral('sysctrl', 0x44900000, 0x1000))
 Reg('time', 0x44900084)
 FieldBit('time_greater_on_bit12', 0)
-Reg("sysctrl_r68", 0x44900068) # set to 0x8000000c for init
-Reg("sysctrl_re0", 0x449000e0) # or with 0x1ff00
-Field("set1", (~0x1ff00) & 0xffffffff)
+Reg("diag_conf", 0x44900068) # set to 0x8000000c for init
+Field("diag_sel", 0xffff0000)
 
+Reg("misc_cntl", 0x449000e0) # or with 0x1ff00
+Field("set1", (~0x1ff00) & 0xffffffff)
 
-## two regs for helper_record_all_states
-Reg("r068", 0x44900068)
-Field("set14", 0xffff0000)
 
-Reg("r074", 0x44900068) # set to b09
+Reg("r074", 0x44900074) # set to b09
 
 #open('../src/include/phy/sysctrl.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))
@@ -410,7 +410,7 @@ def getregs(fname, pattern='name'):
 ## wtf is this???
 
 peris['sysctrl92'] = Peripheral(peripheral('sysctrl92', 0x44920000, 0x1000))
-Reg("set5010001f", 0x44920004)
+Reg("ptr_config", 0x44920004)
 
 #open('../src/include/phy/sysctrl92.h', 'w').write('\n'.join(GenHeader()))
 #print('\n'.join(GenHeader()))

diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h
@@ -112,7 +112,7 @@ typedef union {
 		union {
 			uint32_t value;
 			struct {
-				uint32_t set1 : 2; // @ 1 -- 0 # 0xfffffffc
+				uint32_t combpathsel : 2; // @ 1 -- 0 # 0xfffffffc
 				uint32_t pad0 : 6;
 				uint32_t riu_rifsdeten : 1; // @ 8 -- 8 # 0xfffffeff
 				uint32_t pad1 : 1;
@@ -183,8 +183,8 @@ typedef union {
 				uint32_t pad0 : 8;
 				uint32_t needreset : 1; // @ 8 -- 8 # 0xfffffeff
 			};
-		} r41c; // @ 0x41c
-		uint32_t r420_copy41c; // @ 0x420
+		} rwnxmacintstatmasked; // @ 0x41c
+		uint32_t rwnxmacintack; // @ 0x420
 		uint8_t pad9[0xdc];
 		union {
 			uint32_t value;
@@ -223,7 +223,7 @@ typedef union {
 		union {
 			uint32_t value;
 			struct {
-				uint32_t set0 : 16; // @ 15 -- 0 # 0xffff0000
+				uint32_t txhbf20coeffsel : 16; // @ 15 -- 0 # 0xffff0000
 			};
 		} rc218; // @ 0x1218
 		uint8_t pad14[0x5f8];

diff --git a/src/include/phy/dma.h b/src/include/phy/dma.h
@@ -7,7 +7,7 @@ typedef union {
 			uint32_t value;
 			struct {
 				uint32_t pad0 : 16;
-				uint32_t busyatffff : 16; // @ 31 -- 16 # 0xffff
+				uint32_t dma_status_oft_free : 16; // @ 31 -- 16 # 0xffff
 			};
 		} dma_status; // @ 0x10
 		uint8_t pad1[0xc];
@@ -21,7 +21,7 @@ typedef union {
 				uint32_t b8 : 1; // @ 8 -- 8 # 0xfffffeff
 				uint32_t TX : 27; // @ 31 -- 5 # 0x1f
 			};
-		} tx_reset; // @ 0x20
+		} int_ack; // @ 0x20
 		union {
 			uint32_t value;
 			struct {
@@ -32,7 +32,7 @@ typedef union {
 				uint32_t b8 : 1; // @ 8 -- 8 # 0xfffffeff
 				uint32_t TX : 27; // @ 31 -- 5 # 0x1f
 			};
-		} status; // @ 0x24
+		} int_status; // @ 0x24
 		uint8_t pad2[0x58];
 		union {
 			uint32_t value;
@@ -68,14 +68,14 @@ typedef union {
 		union {
 			uint32_t value;
 			struct {
-				uint32_t lli : 16; // @ 15 -- 0 # 0xffff0000
+				uint32_t counter : 16; // @ 15 -- 0 # 0xffff0000
 			};
 		} LinkListItem0; // @ 0xa4
 		uint8_t pad4[0x4];
 		union {
 			uint32_t value;
 			struct {
-				uint32_t lli : 16; // @ 15 -- 0 # 0xffff0000
+				uint32_t counter : 16; // @ 15 -- 0 # 0xffff0000
 			};
 		} LinkListItem1; // @ 0xac
 	};

diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h
@@ -8,14 +8,14 @@ typedef union {
 				uint32_t pad0 : 4;
 				uint32_t ntx : 4; // @ 7 -- 4 # 0xffffff0f
 				uint32_t nss : 4; // @ 11 -- 8 # 0xfffff0ff
-				uint32_t rxndpnstsmax : 4; // @ 15 -- 12 # 0xffff0fff
+				uint32_t nsts : 4; // @ 15 -- 12 # 0xffff0fff
 				uint32_t pad1 : 2;
-				uint32_t v18 : 1; // @ 18 -- 18 # 0xfffbffff
-				uint32_t v19 : 1; // @ 19 -- 19 # 0xfff7ffff
+				uint32_t ldpcenc : 1; // @ 18 -- 18 # 0xfffbffff
+				uint32_t ldpcdec : 1; // @ 19 -- 19 # 0xfff7ffff
 				uint32_t pad2 : 2;
 				uint32_t vht : 1; // @ 22 -- 22 # 0xffbfffff
 				uint32_t pad3 : 1;
-				uint32_t txcbwmax : 2; // @ 25 -- 24 # 0xfcffffff
+				uint32_t chbw : 2; // @ 25 -- 24 # 0xfcffffff
 				uint32_t ldpctx : 1; // @ 26 -- 26 # 0xfbffffff
 				uint32_t ldpcrx : 1; // @ 27 -- 27 # 0xf7ffffff
 				uint32_t bfmee_supported : 1; // @ 28 -- 28 # 0xefffffff
@@ -49,18 +49,18 @@ typedef union {
 		union {
 			uint32_t value;
 			struct {
-				uint32_t reset : 1; // @ 0 -- 0 # 0xfffffffe
-				uint32_t vht : 1; // @ 1 -- 1 # 0xfffffffd
+				uint32_t rxdsssen : 1; // @ 0 -- 0 # 0xfffffffe
+				uint32_t rxvhten : 1; // @ 1 -- 1 # 0xfffffffd
 				uint32_t pad0 : 2;
 				uint32_t rxnssmax : 3; // @ 6 -- 4 # 0xffffff8f
 				uint32_t pad1 : 1;
-				uint32_t v19 : 1; // @ 8 -- 8 # 0xfffffeff
+				uint32_t rxldpcen : 1; // @ 8 -- 8 # 0xfffffeff
 				uint32_t pad2 : 3;
 				uint32_t rxndpnstsmax : 3; // @ 14 -- 12 # 0xffff8fff
 				uint32_t pad3 : 1;
-				uint32_t v30 : 1; // @ 16 -- 16 # 0xfffeffff
+				uint32_t rxmumimoen : 1; // @ 16 -- 16 # 0xfffeffff
 				uint32_t pad4 : 3;
-				uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff
+				uint32_t rxmumimoapeplenen : 1; // @ 20 -- 20 # 0xffefffff
 				uint32_t pad5 : 3;
 				uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff
 			};
@@ -73,9 +73,9 @@ typedef union {
 				uint32_t pad1 : 2;
 				uint32_t txnssmax : 3; // @ 6 -- 4 # 0xffffff8f
 				uint32_t pad2 : 1;
-				uint32_t v18 : 1; // @ 8 -- 8 # 0xfffffeff
+				uint32_t txldpcen : 1; // @ 8 -- 8 # 0xfffffeff
 				uint32_t pad3 : 7;
-				uint32_t v31 : 1; // @ 16 -- 16 # 0xfffeffff
+				uint32_t txmumimoen : 1; // @ 16 -- 16 # 0xfffeffff
 				uint32_t pad4 : 3;
 				uint32_t ntxmax : 3; // @ 22 -- 20 # 0xff8fffff
 				uint32_t pad5 : 1;
@@ -93,12 +93,12 @@ typedef union {
 		union {
 			uint32_t value;
 			struct {
-				uint32_t set1 : 1; // @ 0 -- 0 # 0xfffffffe
+				uint32_t rxtdctrl1 : 1; // @ 0 -- 0 # 0xfffffffe
 				uint32_t pad0 : 23;
-				uint32_t set60h : 8; // @ 31 -- 24 # 0xffffff
+				uint32_t tddchtstfmargin : 8; // @ 31 -- 24 # 0xffffff
 			};
 		} r834; // @ 0x834
-		uint32_t TXCTRL0; // @ 0x838
+		uint32_t txstartdelay; // @ 0x838
 		uint32_t rxctrl1; // @ 0x83c
 		uint8_t pad3[0x18];
 		union {
@@ -114,7 +114,7 @@ typedef union {
 			uint32_t value;
 			struct {
 				uint32_t pad0 : 27;
-				uint32_t resetto1 : 1; // @ 27 -- 27 # 0xf7ffffff
+				uint32_t rcclkforce : 1; // @ 27 -- 27 # 0xf7ffffff
 				uint32_t pad1 : 1;
 				uint32_t mdm_agcmemclkforce : 1; // @ 29 -- 29 # 0xdfffffff
 			};
@@ -132,9 +132,9 @@ typedef union {
 				uint32_t AGCSWRESET : 1; // @ 12 -- 12 # 0xffffefff
 			};
 		} swreset; // @ 0x888
-		uint32_t TXCTRL1; // @ 0x88c
+		uint32_t txctrl1; // @ 0x88c
 		uint8_t pad7[0x8];
-		uint32_t TXCTRL3; // @ 0x898
+		uint32_t txctrl3; // @ 0x898
 		uint32_t rxframeviolationmask; // @ 0x89c
 		uint8_t pad8[0x2784];
 		union {

diff --git a/src/include/phy/sysctrl.h b/src/include/phy/sysctrl.h
@@ -6,24 +6,26 @@ typedef union {
 		union {
 			uint32_t value;
 			struct {
-				uint32_t set14 : 16; // @ 15 -- 0 # 0xffff0000
+				uint32_t diag_sel : 16; // @ 15 -- 0 # 0xffff0000
 			};
-		} sysctrl_r68; // @ 0x68
-		uint8_t pad1[0x18];
+		} diag_conf; // @ 0x68
+		uint8_t pad1[0x8];
+		uint32_t r074; // @ 0x74
+		uint8_t pad2[0xc];
 		union {
 			uint32_t value;
 			struct {
 				uint32_t time_greater_on_bit12 : 1; // @ 0 -- 0 # 0xfffffffe
 			};
 		} time; // @ 0x84
-		uint8_t pad2[0x58];
+		uint8_t pad3[0x58];
 		union {
 			uint32_t value;
 			struct {
 				uint32_t pad0 : 8;
 				uint32_t set1 : 9; // @ 16 -- 8 # 0xfffe00ff
 			};
-		} sysctrl_re0; // @ 0xe0
+		} misc_cntl; // @ 0xe0
 	};
 } sysctrl_regs;
 #define SYSCTRL_BASE 0x44900000

diff --git a/src/include/phy/sysctrl92.h b/src/include/phy/sysctrl92.h
@@ -3,7 +3,7 @@ typedef union {
 	uint8_t pad[0x1000];
 	struct {
 		uint8_t pad0[0x4];
-		uint32_t set5010001f; // @ 0x4
+		uint32_t ptr_config; // @ 0x4
 	};
 } sysctrl92_regs;
 #define SYSCTRL92_BASE 0x44920000