Align hyper drivers and models to fpga, add barrier for asyncronous r…

…am test
pulp-platform · Mar 9, 2021 · 877b0a2 · 877b0a2
1 parent 405fc7d
commit 877b0a2
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Showing 5 changed files with 64 additions and 60 deletions.
diff --git a/rtos/pulpos/pulp/drivers/hyperbus/hyperbus-v3.c b/rtos/pulpos/pulp/drivers/hyperbus/hyperbus-v3.c
@@ -29,9 +29,15 @@ static PI_L2 pos_udma_channel_t hyper_rx_channel;
 static void pos_hyper_setup(pos_hyper_t *hyper)
 {
   if (hyper->type == PI_HYPER_TYPE_FLASH)
+  {
     plp_hyper_setup(hyper->hyper_id, CONFIG_HYPERFLASH_EN_LATENCY_ADD, hyper->cs, CONFIG_HYPERFLASH_T_LATENCY_ACCESS);
+    plp_hyper_set_reg(UDMA_HYPER_BASE_ADDR(0) + REG_PAGE_BOUND, 0x04);
+  }
   else if (hyper->type == PI_HYPER_TYPE_RAM)
+  {
     plp_hyper_setup(hyper->hyper_id, CONFIG_HYPERRAM_EN_LATENCY_ADD, hyper->cs, CONFIG_HYPERRAM_T_LATENCY_ACCESS);
+    plp_hyper_set_reg(UDMA_HYPER_BASE_ADDR(0) + REG_PAGE_BOUND, 0x03);
+  }
 }
 
 static void pos_hyper_wait_done(pos_hyper_t *hyper)
@@ -135,33 +141,23 @@ int32_t pi_hyper_open(struct pi_device *device)
   hyper->cs = cs;
   hyper->tran_id = 0;
 
-  hyper->open_count = &hyper_open_count;
   hyper->rx_channel = &hyper_rx_channel;
   hyper->tx_channel = &hyper_tx_channel;
 
   device->data = (void *)hyper;
 
   if (hyper_open_count == 0)
   {
-    pos_hyper_create_channel(hyper->rx_channel, UDMA_CHANNEL_ID(periph_id), hyper_channel);
-    pos_hyper_create_channel(hyper->tx_channel, UDMA_CHANNEL_ID(periph_id)+1, hyper_channel+1);
-    // pos_udma_create_channel(hyper->rx_channel, UDMA_CHANNEL_ID(periph_id), hyper_channel);
-    // pos_udma_create_channel(hyper->tx_channel, UDMA_CHANNEL_ID(periph_id)+1, hyper_channel+1);
+    pos_hyper_create_channel(hyper->rx_channel, UDMA_CHANNEL_ID(periph_id), hyper_channel + ARCHI_UDMA_HYPER_EOT_RX_EVT);
+    pos_hyper_create_channel(hyper->tx_channel, UDMA_CHANNEL_ID(periph_id)+1, hyper_channel + ARCHI_UDMA_HYPER_EOT_TX_EVT);
   }
 
   hyper_open_count++;
 
-  hyper->channel = &hyper_channel;
-
   plp_udma_cg_set(plp_udma_cg_get() | (1<<periph_id));
 
-  soc_eu_fcEventMask_setEvent(hyper_channel);
-  soc_eu_fcEventMask_setEvent(hyper_channel+1);
-
-  // soc_eu_prEventMask_setEvent(hyper_channel);
-  // soc_eu_prEventMask_setEvent(hyper_channel+1);
-
-  pos_hyper_setup(hyper);
+  soc_eu_fcEventMask_setEvent(hyper_channel+ ARCHI_UDMA_HYPER_EOT_RX_EVT);
+  soc_eu_fcEventMask_setEvent(hyper_channel + ARCHI_UDMA_HYPER_EOT_TX_EVT);
 
   hal_irq_restore(irq);
 
@@ -286,7 +282,7 @@ void pi_hyper_read_async(struct pi_device *device, uint32_t hyper_addr, void *ad
   unsigned int twd_cmd[HYPER_NB_TWD_REGS] = {0,0,0,0,0,0};
   unsigned int ctl_cmd[HYPER_NB_CTL_REGS] = {0x5, hyper_addr};
 
-  pi_hyper_set_regs(device, PI_HYPER_MEM_SEL, &hyper->cs);
+  pos_hyper_setup(hyper);
 
   hyper->tran_id = plp_hyper_id_alloc(hyper->hyper_id);
 
@@ -308,18 +304,15 @@ void pi_hyper_write(struct pi_device *device, uint32_t hyper_addr, void *addr, u
   unsigned int twd_cmd[HYPER_NB_TWD_REGS] = {0,0,0,0,0,0};
   unsigned int ctl_cmd[HYPER_NB_CTL_REGS] = {0x0, hyper_addr};
 
-  while(plp_hyper_nb_tran(hyper->hyper_id, hyper->tran_id)>HYPER_FIFO_DEPTH-1){}
+  pos_hyper_setup(hyper);
 
-  pi_hyper_set_regs(device, PI_HYPER_MEM_SEL, &hyper->cs);
+  while(plp_hyper_nb_tran(hyper->hyper_id, hyper->tran_id)>HYPER_FIFO_DEPTH-1){}
 
   pi_hyper_set_regs(device, PI_HYPER_TWD, (unsigned int *)twd_cmd);
   pi_hyper_set_regs(device, PI_HYPER_CTL, (unsigned int *)ctl_cmd);
   pi_hyper_set_regs(device, PI_HYPER_CFG, (unsigned short *)addr);
 
   plp_hyper_enqueue(UDMA_HYPER_BASE_ADDR(hyper->hyper_id) + UDMA_HYPER_CHANNEL_TX(hyper->tran_id), 0x0, 0x0, UDMA_CHANNEL_CFG_EN | UDMA_CHANNEL_CFG_SIZE_8);
-
-  /* TODO: Extremely slow because waits until protocol delays are finished. It should be done as async without interrupting the programming sequence */
-  plp_hyper_wait(hyper->hyper_id, hyper->tran_id);
 }
 
 void pi_hyper_write_async(struct pi_device *device, uint32_t hyper_addr, void *addr, uint32_t size, struct pi_task *task)
@@ -329,7 +322,7 @@ void pi_hyper_write_async(struct pi_device *device, uint32_t hyper_addr, void *a
   unsigned int twd_cmd[HYPER_NB_TWD_REGS] = {0,0,0,0,0,0};
   unsigned int ctl_cmd[HYPER_NB_CTL_REGS] = {0x1, hyper_addr};
 
-  pi_hyper_set_regs(device, PI_HYPER_MEM_SEL, &hyper->cs);
+  pos_hyper_setup(hyper);
 
   hyper->tran_id = plp_hyper_id_alloc(hyper->hyper_id);
 

diff --git a/rtos/pulpos/pulp_archi/include/archi/udma/hyper/udma_hyper_v3.h b/rtos/pulpos/pulp_archi/include/archi/udma/hyper/udma_hyper_v3.h
@@ -22,11 +22,11 @@
 #ifndef __ARCHI_UDMA_HYPER_V3_H__
 #define __ARCHI_UDMA_HYPER_V3_H__
 
-#define UDMA_HYPER_OFFSET(id)          UDMA_PERIPH_OFFSET(ARCHI_UDMA_HYPER_ID(id))
-#define UDMA_HYPER_BASE_ADDR(id)       (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id))
-#define UDMA_HYPER_RX_ADDR(id)         (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_RX_OFFSET)
-#define UDMA_HYPER_TX_ADDR(id)         (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_TX_OFFSET)
-#define UDMA_HYPER_CUSTOM_ADDR(id)     (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET(id) + UDMA_CHANNEL_CUSTOM_OFFSET)
+#define UDMA_HYPER_OFFSET(id)          UDMA_PERIPH_OFFSET(ARCHI_UDMA_HYPER_ID((id)))
+#define UDMA_HYPER_BASE_ADDR(id)       (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET((id)))
+#define UDMA_HYPER_RX_ADDR(id)         (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET((id)) + UDMA_CHANNEL_RX_OFFSET)
+#define UDMA_HYPER_TX_ADDR(id)         (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET((id)) + UDMA_CHANNEL_TX_OFFSET)
+#define UDMA_HYPER_CUSTOM_ADDR(id)     (ARCHI_UDMA_ADDR + UDMA_HYPER_OFFSET((id)) + UDMA_CHANNEL_CUSTOM_OFFSET)
 
 /* How many devices in the same hyperchip: cs=0 HyperRam, cs=1 HyperFlash
 */
@@ -37,7 +37,7 @@
 #define HYPER_NB_CHANNELS 4 /* 4 tran_id and 1 common space */
 
 #define HYPER_CHANNELS_OFFSET 0x80
-#define HYPER_CHANNELS_ID_OFFSET(id) HYPER_CHANNELS_OFFSET*id
+#define HYPER_CHANNELS_ID_OFFSET(id) HYPER_CHANNELS_OFFSET*(id)
 #define HYPER_COMMON_REGS_OFFSET HYPER_CHANNELS_OFFSET*HYPER_NB_CHANNELS
 
 #define HYPER_NB_COMMON_REGS 10
@@ -53,14 +53,20 @@
 #define HYPER_BUSY_SIZE 1
 #define HYPER_NB_TRAN_SIZE 8
 
-/* From data path */
+/* From data path
+*/
 #define ARCHI_UDMA_HYPER_RX_EVT           0
 #define ARCHI_UDMA_HYPER_TX_EVT           1
-#define ARCHI_SOC_EVENT_HYPER_RX(id)   (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_RX_EVT)
-#define ARCHI_SOC_EVENT_HYPER_TX(id)   (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_TX_EVT)
-/* From command path */
-#define ARCHI_UDMA_HYPER_CTL_EVT 		  2
-#define ARCHI_SOC_EVENT_HYPER_CTL(id)  (ARCHI_SOC_EVENT_PERIPH_FIRST_EVT(ARCHI_UDMA_HYPER_ID(id)) + ARCHI_UDMA_HYPER_CTL_EVT) 
+/* From command path
+*/
+#define ARCHI_UDMA_HYPER_EOT_RX_EVT       2
+#define ARCHI_UDMA_HYPER_EOT_TX_EVT       3
+
+
+#define ARCHI_SOC_EVENT_HYPER_RX      28
+#define ARCHI_SOC_EVENT_HYPER_TX      29
+#define ARCHI_SOC_EVENT_HYPER_EOT_RX  30
+#define ARCHI_SOC_EVENT_HYPER_EOT_TX  31
 
 
 /* Common registers offsets
@@ -120,27 +126,27 @@
 
 /* Configuration registers
 */
-#define UDMA_HYPER_CHANNEL_RX(id) UDMA_HYPER_CHANNEL_RX_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define UDMA_HYPER_CHANNEL_TX(id) UDMA_HYPER_CHANNEL_TX_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define UDMA_HYPER_CHANNEL_CUSTOM(id) UDMA_HYPER_CHANNEL_CUSTOM_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-
-#define REG_RX_SADDR(id) REG_RX_SADDR_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define REG_RX_SIZE(id) REG_RX_SIZE_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define REG_RX_CFG(id) REG_RX_CFG_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-
-#define REG_TX_SADDR(id) REG_TX_SADDR_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define REG_TX_SIZE(id) REG_TX_SIZE_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define REG_TX_CFG(id) REG_TX_CFG_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-
-#define HYPER_CA_SETUP(id) HYPER_CA_SETUP_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define REG_HYPER_ADDR(id) REG_HYPER_ADDR_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define REG_HYPER_CFG(id) REG_HYPER_CFG_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define STATUS(id) STATUS_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define TWD_ACT(id) TWD_ACT_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define TWD_COUNT(id) TWD_COUNT_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define TWD_STRIDE(id) TWD_STRIDE_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define TWD_ACT_L2(id) TWD_ACT_L2_OFFSET  + HYPER_CHANNELS_ID_OFFSET(id)
-#define TWD_COUNT_L2(id) TWD_COUNT_L2_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
-#define TWD_STRIDE_L2(id) TWD_STRIDE_L2_OFFSET + HYPER_CHANNELS_ID_OFFSET(id)
+#define UDMA_HYPER_CHANNEL_RX(id) UDMA_HYPER_CHANNEL_RX_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define UDMA_HYPER_CHANNEL_TX(id) UDMA_HYPER_CHANNEL_TX_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define UDMA_HYPER_CHANNEL_CUSTOM(id) UDMA_HYPER_CHANNEL_CUSTOM_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+
+#define REG_RX_SADDR(id) REG_RX_SADDR_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define REG_RX_SIZE(id) REG_RX_SIZE_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define REG_RX_CFG(id) REG_RX_CFG_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+
+#define REG_TX_SADDR(id) REG_TX_SADDR_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define REG_TX_SIZE(id) REG_TX_SIZE_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define REG_TX_CFG(id) REG_TX_CFG_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+
+#define HYPER_CA_SETUP(id) HYPER_CA_SETUP_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define REG_HYPER_ADDR(id) REG_HYPER_ADDR_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define REG_HYPER_CFG(id) REG_HYPER_CFG_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define STATUS(id) STATUS_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define TWD_ACT(id) TWD_ACT_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define TWD_COUNT(id) TWD_COUNT_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define TWD_STRIDE(id) TWD_STRIDE_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define TWD_ACT_L2(id) TWD_ACT_L2_OFFSET  + HYPER_CHANNELS_ID_OFFSET((id))
+#define TWD_COUNT_L2(id) TWD_COUNT_L2_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
+#define TWD_STRIDE_L2(id) TWD_STRIDE_L2_OFFSET + HYPER_CHANNELS_ID_OFFSET((id))
 
 #endif
diff --git a/tests/perf/double_buffering/test.c b/tests/perf/double_buffering/test.c
@@ -117,6 +117,9 @@ int main()
         pi_ram_write_async(&ram, hyper_buff+i_prev*N_BYTE, &tempC[N_WORD*(1-buffer_id)], (uint32_t) N_BYTE, pi_task_callback(&ram_write_tasks[i_prev], end_of_tx, NULL));
         task_VectProdScalar(A[i_curr], B, &tempC[N_WORD*buffer_id], N_WORD);
         i_prev++;
+        while(ram_returns != i_curr) {
+            pi_yield();
+        }
     }
     pi_ram_write_async(&ram, hyper_buff+i_prev*N_BYTE, &tempC[N_WORD*buffer_id], (uint32_t) N_BYTE, pi_task_callback(&ram_write_tasks[i_prev], end_of_tx, NULL));    // last transfer
 

diff --git a/tools/gvsoc/pulp/models/pulp/udma/hyper/udma_hyper_v3.cpp b/tools/gvsoc/pulp/models/pulp/udma/hyper/udma_hyper_v3.cpp
@@ -202,10 +202,14 @@ void Hyper_periph_v3::handle_pending_word(void *__this, vp::clock_event *event)
     {
       _this->set_busy_reg(_this->channel_id, 0);
       _this->common_regs[(TRANS_ID_ALLOC_OFFSET)/4] = _this->update_trans_id_alloc();
-      if(_this->command_mode)
+      _this->trace.msg("Current transfer is finished\n");
+      if (!_this->ca.read)
+      {
+        _this->top->trigger_event(ARCHI_SOC_EVENT_HYPER_EOT_TX);
+      }
+      else
       {
-        _this->trace.msg("Current transfer is finished\n");
-        _this->top->trigger_event(ARCHI_UDMA_HYPER_CTL_EVT);
+        _this->top->trigger_event(ARCHI_SOC_EVENT_HYPER_EOT_RX);
       }
     }
     _this->ending = false;

diff --git a/tools/gvsoc/pulp/models/pulp/udma/udma_v3_impl.cpp b/tools/gvsoc/pulp/models/pulp/udma/udma_v3_impl.cpp
@@ -186,12 +186,10 @@ void Udma_channel::check_state()
 
   if (free_reqs->is_full())
   {
-    trace.msg("Inactive\n");;
     this->state_event.event(NULL);
   }
   else
   {
-    trace.msg("Active\n");;
     uint8_t one = 1;
     this->state_event.event(&one);
   }