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add vwc support. fix a tiny unfound bug(without harm).
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@@ -3,3 +3,4 @@ template/* | |
!template/Vivadofile | ||
!template/*.xdc | ||
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*.bit |
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@@ -1,13 +1,37 @@ | ||
# Optional options | ||
# vivado_exec="/home/recolic/extraDisk/xilinx/Vivado/2018.1/bin/vivado" | ||
thread_num=4 | ||
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# | ||
# Required options | ||
# | ||
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# You may use SystemVerilog, Verilog, or VHDL files as sources. | ||
# sources=(test_main.sv lib/* ./mod?.v) | ||
sources=(test_main.sv lib/* ./mod?.v) | ||
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# The directory where generated bitstream is put | ||
bit_dir=./build | ||
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# All of your top_modules and its constraint files. | ||
# top_modules=( | ||
# "test_main:constraint/test_main.xdc" | ||
# "mod1:constraint/mod1.vwc" | ||
# ) | ||
top_modules=( | ||
"test_main:constraint/test_main.xdc" | ||
"mod1:constraint/mod1.xdc" | ||
"mod1:constraint/mod1.vwc" | ||
) | ||
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# Your default top_module. Maybe override by commandline option. | ||
# top_module=test_main | ||
top_module=test_main | ||
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# Name of your board in vivado. HUST uses 'xc7a100tcsg324-1' by default. | ||
board="xc7a100tcsg324-1" | ||
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# | ||
# Optional options | ||
# | ||
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# Path to vivado executable. It will override environment variable `vivado_exec` | ||
# vivado_exec="/path/to/vivado" | ||
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# It's recommanded to set thread_num to cores of your CPU. | ||
thread_num=4 |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,2 @@ | ||
vwc_port P4 i | ||
vwc_port T8 j |
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