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IntelliJ-IDEA-Tutorial Public
Forked from judasn/IntelliJ-IDEA-TutorialIntelliJ IDEA 简体中文专题教程
GNU General Public License v2.0 UpdatedAug 8, 2021 -
verilator Public
Forked from verilator/verilatorVerilator open-source SystemVerilog simulator and lint system
C++ GNU Lesser General Public License v3.0 UpdatedAug 4, 2021 -
oscpu-framework Public
Forked from xuezhen22/oscpu-frameworkA Verilator-based demo.
Verilog UpdatedAug 2, 2021 -
XiangShan Public
Forked from OpenXiangShan/XiangShanOpen-source high-performance RISC-V processor
Scala Other UpdatedAug 1, 2021 -
cocotb Public
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Python Other UpdatedJul 28, 2021 -
NutShell Public
Forked from OSCPU/NutShellRISC-V SoC designed by students in UCAS
Scala Other UpdatedJul 28, 2021 -
core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedJul 21, 2021 -
cv32e40x Public
Forked from openhwgroup/cv32e40x4 stage, in-order, compute RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedJul 21, 2021 -
chisel3 Public
Forked from chipsalliance/chiselChisel 3: A Modern Hardware Design Language
Scala Apache License 2.0 UpdatedJul 20, 2021 -
uarch-bench Public
Forked from travisdowns/uarch-benchA benchmark for low-level CPU micro-architectural features
C++ MIT License UpdatedJul 7, 2021 -
chisel-bootcamp Public
Forked from freechipsproject/chisel-bootcampGenerator Bootcamp Material: Learn Chisel the Right Way
Jupyter Notebook Apache License 2.0 UpdatedJun 27, 2021 -
riffa Public
Forked from KastnerRG/riffaThe RIFFA development repository
Verilog Other UpdatedJun 24, 2021 -
chisel-book Public
Forked from schoeberl/chisel-bookDigital Design with Chisel
TeX UpdatedMay 18, 2021 -
corundum Public
Forked from corundum/corundumOpen source, high performance, FPGA-based NIC
Verilog Other UpdatedApr 2, 2021 -
uvm-python Public
Forked from tpoikela/uvm-pythonUVM 1.2 port to Python
Python Apache License 2.0 UpdatedMar 27, 2021 -
iverilog Public
Forked from steveicarus/iverilogIcarus Verilog
C++ GNU Lesser General Public License v2.1 UpdatedMay 31, 2020 -
tagbar Public
Forked from preservim/tagbarVim plugin that displays tags in a window, ordered by scope
Vim Script Other UpdatedApr 27, 2019 -
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MVision Public
Forked from Ewenwan/MVision机器人视觉 移动机器人 VS-SLAM ORB-SLAM2 深度学习目标检测 yolov3 行为检测 opencv PCL 机器学习 无人驾驶
C++ UpdatedMar 8, 2019 -
acrn-kernel Public
Forked from projectacrn/acrn-kernelKernel tree for ACRN
C Other UpdatedFeb 27, 2019 -
documentation Public
Forked from kata-containers/documentationKata Containers documentation
Shell Apache License 2.0 UpdatedFeb 27, 2019 -
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tvm Public
Forked from apache/tvmOpen deep learning compiler stack for cpu, gpu and specialized accelerators
Python Apache License 2.0 UpdatedDec 11, 2018 -
pp4fpgas-cn Public
Forked from xupsh/pp4fpgas-cn中文版 Parallel Programming for FPGAs
CSS UpdatedDec 8, 2018 -
vimrc Public
Forked from leeehui/vimrcThe ultimate Vim configuration: vimrc
Vim Script MIT License UpdatedDec 3, 2018 -
riffa2 Public
Forked from buttercutter/riffa2Full duplex version of https://github.com/KastnerRG/riffa/issues/30
Verilog Other UpdatedOct 23, 2018 -
SDSOC_CV_ML Public
Forked from XDF2018/SDSOC_CV_MLSDSoC, Computer Vision and Machine Learning
Makefile UpdatedOct 16, 2018 -