Merge pull request #539 from calebstewart/master

Expose configuration of the SEVONPEND bit within the System Control Register (SCR)

cortex-m/src/peripheral/scb.rs

@@ -832,6 +832,26 @@ impl SCB {
     }
 }
 
+const SCB_SCR_SEVONPEND: u32 = 0x1 << 4;
+
+impl SCB {
+    /// Set the SEVONPEND bit in the SCR register
+    #[inline]
+    pub fn set_sevonpend(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr | SCB_SCR_SEVONPEND);
+        }
+    }
+
+    /// Clear the SEVONPEND bit in the SCR register
+    #[inline]
+    pub fn clear_sevonpend(&mut self) {
+        unsafe {
+            self.scr.modify(|scr| scr & !SCB_SCR_SEVONPEND);
+        }
+    }
+}
+
 const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
 const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x7 << 8;
 const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;