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Auto merge of #53822 - dvc94ch:riscv, r=japaric
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[RISCV] Use lld as the default linker; Enable C extension; Add riscv32imc-unknown-none-elf target

The riscv32imc-unknown-none-elf target is intended for soft cores.

The riscv32imc target is supported by the following popular soft cores:

picorv32: https://github.com/cliffordwolf/picorv32
vexriscv: https://github.com/SpinalHDL/VexRiscv
pulp riscy: https://github.com/pulp-platform/riscv
pulp zero-riscy: https://github.com/pulp-platform/zero-riscy
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bors committed Sep 1, 2018
2 parents b7e4402 + 173c679 commit e6381a7
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Showing 6 changed files with 82 additions and 18 deletions.
1 change: 1 addition & 0 deletions src/ci/docker/dist-various-1/Dockerfile
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ ENV TARGETS=$TARGETS,thumbv6m-none-eabi
ENV TARGETS=$TARGETS,thumbv7m-none-eabi
ENV TARGETS=$TARGETS,thumbv7em-none-eabi
ENV TARGETS=$TARGETS,thumbv7em-none-eabihf
ENV TARGETS=$TARGETS,riscv32imc-unknown-none-elf
ENV TARGETS=$TARGETS,riscv32imac-unknown-none-elf
ENV TARGETS=$TARGETS,armebv7r-none-eabi
ENV TARGETS=$TARGETS,armebv7r-none-eabihf
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2 changes: 2 additions & 0 deletions src/librustc_target/spec/mod.rs
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Expand Up @@ -74,6 +74,7 @@ mod thumb_base;
mod l4re_base;
mod fuchsia_base;
mod redox_base;
mod riscv_base;

#[derive(Clone, Copy, Debug, Eq, Ord, PartialEq, PartialOrd, Hash,
RustcEncodable, RustcDecodable)]
Expand Down Expand Up @@ -406,6 +407,7 @@ supported_targets! {
("aarch64-unknown-hermit", aarch64_unknown_hermit),
("x86_64-unknown-hermit", x86_64_unknown_hermit),

("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),

("aarch64-unknown-none", aarch64_unknown_none),
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24 changes: 6 additions & 18 deletions src/librustc_target/spec/riscv32imac_unknown_none_elf.rs
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Expand Up @@ -8,8 +8,8 @@
// option. This file may not be copied, modified, or distributed
// except according to those terms.

use spec::{LinkerFlavor, PanicStrategy, Target, TargetOptions, TargetResult};
use spec::abi::{Abi};
use spec::{LinkerFlavor, LldFlavor, PanicStrategy,
Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
Expand All @@ -22,31 +22,19 @@ pub fn target() -> TargetResult {
target_env: String::new(),
target_vendor: "unknown".to_string(),
arch: "riscv32".to_string(),
linker_flavor: LinkerFlavor::Ld,
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
linker: Some("riscv32-unknown-elf-ld".to_string()),
linker: Some("rust-lld".to_string()),
cpu: "generic-rv32".to_string(),
max_atomic_width: Some(32),
atomic_cas: false, // incomplete +a extension
features: "+m,+a".to_string(), // disable +c extension
features: "+m,+a,+c".to_string(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: "static".to_string(),
emit_debug_gdb_scripts: false,
abi_blacklist: vec![
Abi::Cdecl,
Abi::Stdcall,
Abi::Fastcall,
Abi::Vectorcall,
Abi::Thiscall,
Abi::Aapcs,
Abi::Win64,
Abi::SysV64,
Abi::PtxKernel,
Abi::Msp430Interrupt,
Abi::X86Interrupt,
],
abi_blacklist: super::riscv_base::abi_blacklist(),
.. Default::default()
},
})
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42 changes: 42 additions & 0 deletions src/librustc_target/spec/riscv32imc_unknown_none_elf.rs
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@@ -0,0 +1,42 @@
// Copyright 2018 The Rust Project Developers. See the COPYRIGHT
// file at the top-level directory of this distribution and at
// http://rust-lang.org/COPYRIGHT.
//
// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
// option. This file may not be copied, modified, or distributed
// except according to those terms.

use spec::{LinkerFlavor, LldFlavor, PanicStrategy,
Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".to_string(),
llvm_target: "riscv32".to_string(),
target_endian: "little".to_string(),
target_pointer_width: "32".to_string(),
target_c_int_width: "32".to_string(),
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: "unknown".to_string(),
arch: "riscv32".to_string(),
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
linker: Some("rust-lld".to_string()),
cpu: "generic-rv32".to_string(),
// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005
max_atomic_width: None, //Some(32),
atomic_cas: false,
features: "+m,+c".to_string(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: "static".to_string(),
emit_debug_gdb_scripts: false,
abi_blacklist: super::riscv_base::abi_blacklist(),
.. Default::default()
},
})
}
30 changes: 30 additions & 0 deletions src/librustc_target/spec/riscv_base.rs
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@@ -0,0 +1,30 @@
// Copyright 2018 The Rust Project Developers. See the COPYRIGHT
// file at the top-level directory of this distribution and at
// http://rust-lang.org/COPYRIGHT.
//
// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
// option. This file may not be copied, modified, or distributed
// except according to those terms.

use spec::abi::Abi;

// All the calling conventions trigger an assertion(Unsupported calling
// convention) in llvm on RISCV
pub fn abi_blacklist() -> Vec<Abi> {
vec![
Abi::Cdecl,
Abi::Stdcall,
Abi::Fastcall,
Abi::Vectorcall,
Abi::Thiscall,
Abi::Aapcs,
Abi::Win64,
Abi::SysV64,
Abi::PtxKernel,
Abi::Msp430Interrupt,
Abi::X86Interrupt,
Abi::AmdGpuKernel,
]
}
1 change: 1 addition & 0 deletions src/tools/build-manifest/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -92,6 +92,7 @@ static TARGETS: &'static [&'static str] = &[
"powerpc64-unknown-linux-gnu",
"powerpc64le-unknown-linux-gnu",
"powerpc64le-unknown-linux-musl",
"riscv32imc-unknown-none-elf",
"riscv32imac-unknown-none-elf",
"s390x-unknown-linux-gnu",
"sparc-unknown-linux-gnu",
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