FPGA-Slot-Machine

A slot machine written in Verilog. Built, simulated, synthesized, and implemented in Vivado on the Xilinx Basys 3 Artix-7 FPGA board.

This project was inspired by a recent trip to Vegas.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
README.md		README.md
actual_display.v		actual_display.v
clk_dv.v		clk_dv.v
clk_gradual.v		clk_gradual.v
debounce.v		debounce.v
display.v		display.v
lfsr.v		lfsr.v
random_gen.v		random_gen.v
scoring.v		scoring.v
split_nums.v		split_nums.v
stop.v		stop.v
tb.v		tb.v
tb_score.v		tb_score.v
top.v		top.v

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