Remove case parens, rename jit/gen macros

saiminhtet · Oct 20, 2019 · f2dd138 · f2dd138
1 parent 6b0a00e
commit f2dd138
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Showing 2 changed files with 8 additions and 9 deletions.
diff --git a/emu/decode.h b/emu/decode.h
@@ -117,8 +117,8 @@ __no_instrument DECODER_RET glue(DECODER_NAME, OP_SIZE)(DECODER_ARGS) {
 
                 case 0x73: READMODRM;
                            switch (modrm.opcode) {
-                               case (0x02): TRACEI("psrlq xmm imm");
-                                            READIMM8; VIMM_SHIFTR(xmm_modrm_val, imm,64); break;
+                               case 0x02: TRACEI("psrlq xmm imm");
+                                          READIMM8; VSHIFTR_IMM(xmm_modrm_val, imm,64); break;
                                default: UNDEFINED;
                            }
                            break;

diff --git a/jit/gen.c b/jit/gen.c
@@ -458,31 +458,30 @@ static inline bool gen_vec(enum arg rm, enum arg reg, void (*helper)(), gadget_t
     }
 
     switch (v_rm) {
-        case (vec_arg_reg):
-        case (vec_arg_xmm):
+        case vec_arg_xmm:
             GEN(gadget);
             GEN(helper);
             GEN((modrm->opcode * sizeof(union xmm_reg))
                     | (modrm->rm_opcode * sizeof(union xmm_reg) << 8));
             break;
 
-        case (vec_arg_mem):
+        case vec_arg_mem:
             gen_addr(state, modrm, seg_gs, saved_ip);
             GEN(gadget);
             GEN(saved_ip);
             GEN(helper);
             GEN(modrm->opcode * sizeof(union xmm_reg));
             break;
 
-        case (vec_arg_imm):
+        case vec_arg_imm:
             // TODO: support immediates and opcode
             GEN(gadget);
             GEN(helper);
             GEN((modrm->rm_opcode * sizeof(union xmm_reg))
                     | (((uint16_t) imm) << 8));
             break;
 
-        default: UNDEFINED;
+        default: die("unimplemented vecarg");
     }
     return true;
 }
@@ -496,7 +495,7 @@ static inline bool gen_vec(enum arg rm, enum arg reg, void (*helper)(), gadget_t
     if (!gen_vec(arg_imm, dst, helper, &helper_gadgets, state, &modrm, imm, saved_ip, seg_gs)) return false; \
 } while (0)
 #define v(op, src, dst,z) _v(arg_##src, arg_##dst, vec_##op##z, vec_helper_load##z##_gadgets, z)
-#define vi(op, imm, dst,z) _vi(imm, arg_##dst, vec_##op##z, vec_helper_load##z##_gadgets, z)
+#define v_imm(op, imm, dst,z) _vi(imm, arg_##dst, vec_##op##z, vec_helper_load##z##_gadgets, z)
 #define v_write(op, src, dst,z) _v(arg_##dst, arg_##src, vec_##op##z, vec_helper_store##z##_gadgets, z)
 
 #define VLOAD(src, dst,z) v(load, src, dst,z)
@@ -517,7 +516,7 @@ static inline bool gen_vec(enum arg rm, enum arg reg, void (*helper)(), gadget_t
 } while (0)
 #define VSTORE(src, dst,z) v_write(store, src, dst,z)
 #define VCOMPARE(src, dst,z) v(compare, src, dst,z)
-#define VIMM_SHIFTR(reg, amount, z) vi(imm_shiftr, amount, reg,z)
+#define VSHIFTR_IMM(reg, amount, z) vi(imm_shiftr, amount, reg,z)
 #define VXOR(src, dst,z) v(xor, src, dst,z)
 
 #define DECODER_RET int