changed dramtest to use pcieclk for both dram and hwman

sangwoojun · Jul 15, 2021 · 85c15cf · 85c15cf
1 parent 6b3562f
commit 85c15cf
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Showing 2 changed files with 20 additions and 20 deletions.
diff --git a/examples/dramtest/HwMain.bsv b/examples/dramtest/HwMain.bsv
@@ -23,18 +23,18 @@ module mkHwMain#(PcieUserIfc pcie, DRAMUserIfc dram)
 
 	//DMASplitterIfc#(4) dma <- mkDMASplitter(pcie);
 
-	Reg#(Bit#(32)) cycles <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
+	Reg#(Bit#(32)) cycles <- mkReg(0);
 	rule incCycle;
 		cycles <= cycles + 1;
 	endrule
 
-	FIFO#(Tuple2#(Bit#(16),Bit#(16))) dramReadReqQ <- mkSizedBRAMFIFO(1024, clocked_by pcieclk, reset_by pcierst); // offset, words
-	Reg#(Bit#(16)) dramReadReqCnt <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(16)) dramReadReqDone <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(16)) dramReqWordLeft <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(16)) dramReqWordOff <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) startCycle <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) elapsedCycle <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
+	FIFO#(Tuple2#(Bit#(16),Bit#(16))) dramReadReqQ <- mkSizedBRAMFIFO(1024); // offset, words
+	Reg#(Bit#(16)) dramReadReqCnt <- mkReg(0);
+	Reg#(Bit#(16)) dramReadReqDone <- mkReg(0);
+	Reg#(Bit#(16)) dramReqWordLeft <- mkReg(0);
+	Reg#(Bit#(16)) dramReqWordOff <- mkReg(0);
+	Reg#(Bit#(32)) startCycle <- mkReg(0);
+	Reg#(Bit#(32)) elapsedCycle <- mkReg(0);
 	rule startDRAMRead(dramReadReqCnt >= 1024 && dramReqWordLeft == 0);
 		let r = dramReadReqQ.first;
 		dramReadReqQ.deq;
@@ -43,7 +43,7 @@ module mkHwMain#(PcieUserIfc pcie, DRAMUserIfc dram)
 		dramReadReqDone <= dramReadReqDone + 1;
 		if ( dramReadReqDone == 0 ) startCycle <= cycles;
 	endrule
-	FIFO#(Bool) isLastQ <- mkSizedFIFO(64, clocked_by pcieclk, reset_by pcierst);
+	FIFO#(Bool) isLastQ <- mkSizedFIFO(64);
 	rule issueDRAMRead (dramReqWordLeft > 0 );
 		dramReqWordLeft <= dramReqWordLeft -1;
 		dramReqWordOff <= dramReqWordOff + 1;
@@ -58,13 +58,13 @@ module mkHwMain#(PcieUserIfc pcie, DRAMUserIfc dram)
 	endrule
 
 
-	Reg#(Bit#(32)) wordReadLeft <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) wordWriteLeft <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) wordWriteReq <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) dramWriteLeft <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) dramReadLeft <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) dramWriteStartCycle <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
-	Reg#(Bit#(32)) dramWriteEndCycle <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
+	Reg#(Bit#(32)) wordReadLeft <- mkReg(0);
+	Reg#(Bit#(32)) wordWriteLeft <- mkReg(0);
+	Reg#(Bit#(32)) wordWriteReq <- mkReg(0);
+	Reg#(Bit#(32)) dramWriteLeft <- mkReg(0);
+	Reg#(Bit#(32)) dramReadLeft <- mkReg(0);
+	Reg#(Bit#(32)) dramWriteStartCycle <- mkReg(0);
+	Reg#(Bit#(32)) dramWriteEndCycle <- mkReg(0);
 
 
 
@@ -107,21 +107,21 @@ module mkHwMain#(PcieUserIfc pcie, DRAMUserIfc dram)
 
 		dram.readReq(zeroExtend(dramReadLeft)*64, 64);
 	endrule
-	Reg#(Bit#(512)) dramReadVal <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
+	Reg#(Bit#(512)) dramReadVal <- mkReg(0);
 	rule dramReadResp;
 		let d <- dram.read;
 		dramReadVal <= d;
 	endrule
 
-	Reg#(DMAWord) lastRecvWord <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
+	Reg#(DMAWord) lastRecvWord <- mkReg(0);
 
 	rule recvDMAData;
 		wordReadLeft <= wordReadLeft - 1;
 		let d <- pcie.dmaReadWord;
 		lastRecvWord  <= d;
 	endrule
 
-	Reg#(Bit#(32)) writeData <- mkReg(0, clocked_by pcieclk, reset_by pcierst);
+	Reg#(Bit#(32)) writeData <- mkReg(0);
 	rule sendDMAData ( wordWriteLeft > 0 );
 		pcie.dmaWriteData({writeData+3,writeData+2,writeData+1,writeData});
 		writeData <= writeData + 4;

diff --git a/examples/dramtest/Top.bsv b/examples/dramtest/Top.bsv
@@ -66,7 +66,7 @@ module mkProjectTop #(
 	DDR3_Controller_1GB ddr3_ctrl <- mkDDR3Controller_1GB(ddr3_cfg, ddr_buf, clocked_by ddr_buf, reset_by ddr3ref_rst_n);
 	DRAMControllerIfc dramController <- mkDRAMController(ddr3_ctrl.user, clocked_by pcieCtrl.user.user_clk, reset_by pcieCtrl.user.user_rst);
 
-	HwMainIfc hwmain <- mkHwMain(pcieCtrl.user, dramController.user, clocked_by sys_clk_200mhz_buf, reset_by rst200);
+	HwMainIfc hwmain <- mkHwMain(pcieCtrl.user, dramController.user, clocked_by pcieCtrl.user.user_clk, reset_by pcieCtrl.user.user_rst);