Merge branch 'master' of github.com:sangwoojun/bluespecpcie

distribute/program.sh

@@ -2,7 +2,12 @@ if [ $# -eq 0 ]
 then
 	vivado -mode batch -source /opt/shared/program.tcl -nolog -nojournal
 else
-	vivado -mode batch -source /opt/shared/program.tcl -tclargs $1 -nolog -nojournal
+	if [ $# -eq 1 ]
+	then
+		vivado -mode batch -source /opt/shared/program.tcl  -nolog -nojournal -tclargs $1
+	else
+		vivado -mode batch -source /opt/shared/program.tcl -nolog -nojournal -tclargs $1 $2
+	fi
 fi
 sleep 2
 bsrescan

distribute/program.tcl

@@ -1,15 +1,28 @@
-open_hw
+open_hw_manager
 connect_hw_server
-open_hw_target 
-set fpga [lindex [get_hw_devices] 2] 
+set hwtargets [get_hw_targets]
+
+if { $::argc > 1 } {
+	open_hw_target [lindex [get_hw_targets] [lindex $argv 1] ]
+} else {
+	open_hw_target [lindex [get_hw_targets] 0]
+}
 
 if { $::argc > 0 } {
 	set file [lindex $argv 0]
 } else {
 	set file ./vc707/hw/mkProjectTop.bit
 }
 
-set_property PROGRAM.FILE $file $fpga
-puts "fpga is $fpga, bit file size is [exec ls -sh $file], PROGRAM BEGIN"
-program_hw_devices -verbose $fpga
-refresh_hw_device $fpga
+foreach fpga [get_hw_devices] {
+	if {[string first "xc7vx485t" $fpga] != -1} {
+		puts "fpga is $fpga, bit file size is [exec ls -sh $file], PROGRAM BEGIN"
+
+		set_property PROGRAM.FILE $file $fpga
+		program_hw_devices -verbose $fpga
+		refresh_hw_device $fpga
+		break
+	}
+}
+
+

examples/simple/HwMain.bsv

@@ -67,7 +67,7 @@ module mkHwMain#(PcieUserIfc pcie)
 
 		if ( a == 0 ) begin // command 
 		end else if ( a == 4 ) begin // data load
-			for ( Integer i = 1; i < 16; i++ ) begin
+			for ( Integer i = 1; i < 15; i=i+1 ) begin
 				writeBuffer[i+1] <= writeBuffer[i];
 			end
 			writeBuffer[0] <= d;

src/PcieCtrl.bsv

@@ -244,7 +244,8 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 	FIFO#(Bit#(8)) dmaReadTagOrderQ <- mkSizedBRAMFIFO(128);
 	ByteShiftIfc#(Bit#(128), 7) doneShifter <- mkPipelineLeftShifterBits;
 	ByteShiftIfc#(Bit#(128), 7) orderShifter <- mkPipelineLeftShifterBits;
-	FIFO#(Bit#(8)) orderTagBypassQ <- mkSizedFIFO(8);
+	FIFO#(Bit#(8)) orderTagBypassQ1 <- mkSizedFIFO(8);
+	FIFO#(Bit#(8)) orderTagBypassQ2 <- mkFIFO;
 	Reg#(Bit#(128)) doneTagMap <- mkReg(0);
 	Reg#(Bit#(128)) orderTagMap <- mkReg(0);
 	BRAM2Port#(Bit#(8),Tuple2#(Bit#(8),Bit#(10))) doneMap <- mkBRAM2Server(defaultValue); // tag, total words,words recv
@@ -262,7 +263,11 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 		let tag = dmaReadTagOrderQ.first;
 		dmaReadTagOrderQ.deq;
 		orderShifter.rotateByteBy(1,truncate(tag));
-		orderTagBypassQ.enq(tag);
+		orderTagBypassQ1.enq(tag);
+	endrule
+	rule forwardShiftOrderTagBypass;
+		orderTagBypassQ1.deq;
+		orderTagBypassQ2.enq(orderTagBypassQ1.first);
 	endrule
 	Reg#(Maybe#(Bit#(128))) curOrderTag <- mkReg(tagged Invalid);
 	FIFO#(Bit#(8)) doneReorderedTagQ <- mkFIFO;
@@ -278,8 +283,8 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 				orderTagMap <= orderTagMap ^ ot;
 				curOrderTag <= tagged Invalid;
 
-				let tag = orderTagBypassQ.first;
-				orderTagBypassQ.deq;
+				let tag = orderTagBypassQ2.first;
+				orderTagBypassQ2.deq;
 				doneReorderedTagQ.enq(tag);
 			end
 		end else begin
@@ -290,8 +295,8 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 				orderTagMap <= orderTagMap ^ v;
 				//curOrderTag <= tagged Invalid;
 
-				let tag = orderTagBypassQ.first;
-				orderTagBypassQ.deq;
+				let tag = orderTagBypassQ2.first;
+				orderTagBypassQ2.deq;
 				doneReorderedTagQ.enq(tag);
 			end else begin
 				curOrderTag <= tagged Valid v;