added FIFO1, better timing with pciectrl

buildtools/verilogcopy.sh

@@ -9,6 +9,7 @@ VFILES="
 	SizedFIFO.v
 	Counter.v
 	TriState.v
+	FIFO1.v
 	FIFO2.v
 	ResetInverter.v
 	SyncFIFO.v

examples/simple/HwMain.bsv

@@ -43,10 +43,31 @@ module mkHwMain#(PcieUserIfc pcie)
 		end
 		$display( "Received read req at %x", r.addr );
 	endrule
+
+
+
+	Vector#(16, Reg#(Bit#(32))) writeBuffer <- replicateM(mkReg(0));
+	Reg#(Bit#(4)) writeBufferCnt <- mkReg(0);
+
+
+
 	rule recvWrite;
 		let w <- pcie.dataReceive;
 		let a = w.addr;
 		let d = w.data;
+
+		if ( a == 0 ) begin // command 
+		end else if ( a == 4 ) begin // data load
+			for ( Integer i = 1; i < 16; i++ ) begin
+				writeBuffer[i+1] <= writeBuffer[i];
+			end
+			writeBuffer[0] <= d;
+			if ( writeBufferCnt == 15 ) begin
+				writeBufferCnt <= 0;
+			end else begin
+				writeBufferCnt <= writeBufferCnt + 1;
+			end
+		end
 
 		// PCIe IO is done at 4 byte granularities
 		// lower 2 bits are always zero

src/PcieCtrl.bsv

@@ -824,6 +824,8 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 
 	FIFO#(DMAReq) dmaWriteReqQ <- mkFIFO;
 	FIFO#(DMAWord) dmaWriteWordQ <- mkSizedFIFO(32);
+	Reg#(Bit#(10)) dmaWriteWordIn <- mkReg(0);
+	Reg#(Bit#(10)) dmaWriteWordOut <- mkReg(0);
 	Reg#(DMAWord) dmaWriteBuf <- mkReg(0);
 
 	Reg#(Bit#(32)) dmaStartAddr <- mkReg(0);
@@ -882,7 +884,7 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 
 	//Reg#(Bit#(128)) dataShiftBuffer <- mkReg(0);
 	Reg#(Bit#(10)) dataWordsRemain <- mkReg(0);
-	rule generateHeaderTLP ( dataWordsRemain == 0 );
+	rule generateHeaderTLP ( dataWordsRemain == 0 && dmaWriteWordIn-dmaWriteWordOut >= dmaPageWriteReqQ.first().words );
 
 		//let busAddr <- configBuffer.portB.response.get;
 		let busAddr = dmaWriteBufAddrQ.first;
@@ -899,6 +901,7 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 		dmaWriteWordQ.deq;
 		let data = dmaWriteWordQ.first;
 		dmaWriteBuf <= (data>>32);
+		dmaWriteWordOut <= dmaWriteWordOut + dmaWords;
 
 		Bit#(32) cdw0 = {
 			1'b0,
@@ -1047,6 +1050,7 @@ module mkPcieCtrl#(PcieImportUser user) (PcieCtrlIfc);
 		endmethod
 		method Action dmaWriteData(DMAWord data);
 			dmaWriteWordQ.enq(data);
+			dmaWriteWordIn <= dmaWriteWordIn + 1;
 		endmethod
 		method Action dmaReadReq(Bit#(32) addr, Bit#(10) words);
 			dmaReadReqQ.enq(DMAReq{addr:addr, words:words, tag:?});