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seppel committed Jun 30, 2002
1 parent dd95c86 commit 172945c
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Showing 166 changed files with 19,170 additions and 5,428 deletions.
3 changes: 3 additions & 0 deletions acconfig.h
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Original file line number Diff line number Diff line change
@@ -1,4 +1,7 @@

/* Where is the curses header file ? */
#define CURSES_HDR @CURSES_HDR@

/* Where is the curses header file ? */
#undef HAVE_TEXTMODE_X11
@TOP@
54 changes: 35 additions & 19 deletions asm/alphadis.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -59,34 +59,34 @@
#define MAKE_PAL(opcode) (opcode & 0x3ffffff)
#define MAKE_HINT(opcode) (opcode & 0x3fff)

alphadis::alphadis():disassembler()
Alphadis::Alphadis():Disassembler()
{
insn.valid = false;
}

alphadis::~alphadis()
Alphadis::~Alphadis()
{
}

dis_insn *alphadis::create_invalid_insn()
dis_insn *Alphadis::createInvalidInsn()
{
insn.valid = false;
return &insn;
}

int alphadis::load(ht_object_stream *f)
int Alphadis::load(ht_object_stream *f)
{
return disassembler::load(f);
return Disassembler::load(f);
}

int find_alpha_instruction(opcode_tab_entry *table, int f)
int find_alpha_instruction(alpha_opcode_tab_entry *table, int f)
{
int i=0;
while (f > (table+i)->fcode) i++;
return i;
}

dis_insn *alphadis::decode(byte *code, byte maxlen, CPU_ADDR addr)
dis_insn *Alphadis::decode(byte *code, byte maxlen, CPU_ADDR addr)
{
// alpha code instructions must be 32 bits long
if (maxlen < 4) {
Expand All @@ -95,7 +95,7 @@ dis_insn *alphadis::decode(byte *code, byte maxlen, CPU_ADDR addr)
insn.size = maxlen;
insn.table = 0;
// FIXME: this reads to much bytes!
insn.data = *(dword *)code;
UNALIGNED_MOVE(insn.data, *(dword *)code);
} else {
insn.valid = true;
insn.size = 4;
Expand Down Expand Up @@ -250,34 +250,51 @@ dis_insn *alphadis::decode(byte *code, byte maxlen, CPU_ADDR addr)
return &insn;
}

int alphadis::getmaxopcodelength()
dis_insn *Alphadis::duplicateInsn(dis_insn *disasm_insn)
{
alphadis_insn *insn = (alphadis_insn *)malloc(sizeof (alphadis_insn));
*insn = *(alphadis_insn *)disasm_insn;
return insn;
}

int Alphadis::getMaxOpcodeLength()
{
// alpha opcodes are 32 bits long
return 4;
}

char *alphadis::get_name()
void Alphadis::getOpcodeMetrics(int &min_length, int &max_length, int &min_look_ahead, int &avg_look_ahead, int &addr_align)
{
min_length = 4;
max_length = 4;
min_look_ahead = 4;
avg_look_ahead = 4;
addr_align = 4;
}

char *Alphadis::getName()
{
return "alpha/disassembler";
}

byte alphadis::getsize(dis_insn *disasm_insn)
byte Alphadis::getSize(dis_insn *disasm_insn)
{
return ((alphadis_insn*)disasm_insn)->size;
}

OBJECT_ID alphadis::object_id()
OBJECT_ID Alphadis::object_id()
{
return ATOM_DISASM_ALPHA;
}

void alphadis::store(ht_object_stream *f)
void Alphadis::store(ht_object_stream *f)
{
disassembler::store(f);
Disassembler::store(f);
}

char *alphadis::str(dis_insn *disasm_insn, int style)
char *Alphadis::str(dis_insn *disasm_insn, int style)
{

return strf(disasm_insn, style, "");
}

Expand All @@ -286,7 +303,7 @@ char *alphadis::str(dis_insn *disasm_insn, int style)
#define A_REG_C alpha_reg_names[alpha_insn->regC]
#define A_NAME (alpha_insn->table+alpha_insn->code)->name

char *alphadis::strf(dis_insn *disasm_insn, int style, char *format)
char *Alphadis::strf(dis_insn *disasm_insn, int style, char *format)
{
if (style & DIS_STYLE_HIGHLIGHT) enable_highlighting();

Expand Down Expand Up @@ -362,10 +379,9 @@ char *alphadis::strf(dis_insn *disasm_insn, int style, char *format)
CPU_ADDR caddr;
caddr.addr32.offset = (dword)alpha_insn->data;
int slen;
char *p;
char *s = (addr_sym_func) ? addr_sym_func(caddr, &slen, addr_sym_func_context) : 0;
if (s) {
p = insnstr + sprintf(insnstr, "%-10s %s %s(%s%s%s),%s ", A_NAME, A_REG_A, cs_symbol, cs_default, A_REG_B, cs_symbol, cs_default);
char *p = insnstr + sprintf(insnstr, "%-10s %s %s(%s%s%s),%s ", A_NAME, A_REG_A, cs_symbol, cs_default, A_REG_B, cs_symbol, cs_default);
memmove(p, s, slen);
p[slen] = 0;
} else {
Expand All @@ -383,7 +399,7 @@ char *alphadis::strf(dis_insn *disasm_insn, int style, char *format)
return insnstr;
}

bool alphadis::valid_insn(dis_insn *disasm_insn)
bool Alphadis::validInsn(dis_insn *disasm_insn)
{
return ((alphadis_insn *)disasm_insn)->valid;
}
Expand Down
20 changes: 11 additions & 9 deletions asm/alphadis.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,32 +33,34 @@ struct alphadis_insn {
byte regA;
byte regB;
byte regC;
opcode_tab_entry *table;
alpha_opcode_tab_entry *table;
};

/*
* CLASS alphadis
*/

class alphadis: public disassembler {
class Alphadis: public Disassembler {
protected:
char insnstr[256];
alphadis_insn insn;
public:
alphadis();
virtual ~alphadis();
Alphadis();
virtual ~Alphadis();

virtual dis_insn *create_invalid_insn();
virtual dis_insn *createInvalidInsn();
int load(ht_object_stream *f);
virtual dis_insn *decode(byte *code, byte maxlen, CPU_ADDR addr);
virtual int getmaxopcodelength();
virtual byte getsize(dis_insn *disasm_insn);
virtual char *get_name();
virtual dis_insn *duplicateInsn(dis_insn *disasm_insn);
virtual int getMaxOpcodeLength();
virtual void getOpcodeMetrics(int &min_length, int &max_length, int &min_look_ahead, int &avg_look_ahead, int &addr_align);
virtual byte getSize(dis_insn *disasm_insn);
virtual char *getName();
virtual void store(ht_object_stream *f);
virtual char *str(dis_insn *disasm_insn, int style);
virtual char *strf(dis_insn *disasm_insn, int style, char *format);
virtual OBJECT_ID object_id();
virtual bool valid_insn(dis_insn *disasm_insn);
virtual bool validInsn(dis_insn *disasm_insn);
};

#endif
Expand Down
24 changes: 12 additions & 12 deletions asm/alphaopc.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ char *alpha_reg_names[] = {
};


opcode_tab_entry alpha_instr_tbl[] =
alpha_opcode_tab_entry alpha_instr_tbl[] =
{
{0x00,"call_pal", ALPHA_GROUP_PAL},
{0x01,"opcode01", ALPHA_ERROR},
Expand Down Expand Up @@ -110,7 +110,7 @@ opcode_tab_entry alpha_instr_tbl[] =
};

/* table10 */
opcode_tab_entry alpha_instr_tbl_ext10[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext10[] =
{
{0x00,"addl", ALPHA_GROUP1},
{0x02,"s4addl", ALPHA_GROUP1},
Expand Down Expand Up @@ -138,7 +138,7 @@ opcode_tab_entry alpha_instr_tbl_ext10[] =
};

/* table11 */
opcode_tab_entry alpha_instr_tbl_ext11[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext11[] =
{
{0x00,"and", ALPHA_GROUP1},
{0x08,"bic", ALPHA_GROUP1},
Expand All @@ -160,7 +160,7 @@ opcode_tab_entry alpha_instr_tbl_ext11[] =
};

/* table12 */
opcode_tab_entry alpha_instr_tbl_ext12[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext12[] =
{
{0x00,"", ALPHA_ERROR},
{0x02,"mskbl", ALPHA_GROUP1},
Expand Down Expand Up @@ -193,7 +193,7 @@ opcode_tab_entry alpha_instr_tbl_ext12[] =
};

/* table13 */
opcode_tab_entry alpha_instr_tbl_ext13[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext13[] =
{
{0x00,"mull", ALPHA_GROUP1},
{0x20,"mulq", ALPHA_GROUP1},
Expand All @@ -204,7 +204,7 @@ opcode_tab_entry alpha_instr_tbl_ext13[] =
};

/* table14 */
opcode_tab_entry alpha_instr_tbl_ext14[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext14[] =
{
{0x000,"", ALPHA_ERROR},
{0x004,"itofs", ALPHA_GROUP_I2F},
Expand Down Expand Up @@ -262,7 +262,7 @@ opcode_tab_entry alpha_instr_tbl_ext14[] =
};

/* table15 */
opcode_tab_entry alpha_instr_tbl_ext15[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext15[] =
{
{0x000,"addf/c", ALPHA_GROUP2},
{0x001,"subf/c", ALPHA_GROUP2},
Expand Down Expand Up @@ -374,7 +374,7 @@ opcode_tab_entry alpha_instr_tbl_ext15[] =
};

/* table16 */
opcode_tab_entry alpha_instr_tbl_ext16[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext16[] =
{
{0x000,"adds/c", ALPHA_GROUP2},
{0x001,"subs/c", ALPHA_GROUP2},
Expand Down Expand Up @@ -566,7 +566,7 @@ opcode_tab_entry alpha_instr_tbl_ext16[] =
};

/* table17 */
opcode_tab_entry alpha_instr_tbl_ext17[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext17[] =
{
{0x000,"", ALPHA_ERROR},
{0x010,"cvtlq", ALPHA_GROUP2},
Expand All @@ -588,7 +588,7 @@ opcode_tab_entry alpha_instr_tbl_ext17[] =
};

/* table18 */
opcode_tab_entry alpha_instr_tbl_ext18[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext18[] =
{
{0x0000,"trapb", ALPHA_GROUP3},
{0x0400,"excb", ALPHA_GROUP3},
Expand All @@ -605,7 +605,7 @@ opcode_tab_entry alpha_instr_tbl_ext18[] =
};

/* table1a */
opcode_tab_entry alpha_instr_tbl_ext1a[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext1a[] =
{
{0x0,"jmp", ALPHA_GROUP_JMP},
{0x1,"jsr", ALPHA_GROUP_JMP},
Expand All @@ -615,7 +615,7 @@ opcode_tab_entry alpha_instr_tbl_ext1a[] =
};

/* table1c */
opcode_tab_entry alpha_instr_tbl_ext1c[] =
alpha_opcode_tab_entry alpha_instr_tbl_ext1c[] =
{
{0x00,"sextb", ALPHA_GROUP1},
{0x01,"sextw", ALPHA_GROUP1},
Expand Down
26 changes: 13 additions & 13 deletions asm/alphaopc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,25 +23,25 @@

#include "global.h"

struct opcode_tab_entry {
struct alpha_opcode_tab_entry {
word fcode;
char *name;
byte type;
};

extern char *alpha_reg_names[];
extern opcode_tab_entry alpha_instr_tbl[];
extern opcode_tab_entry alpha_instr_tbl_ext10[];
extern opcode_tab_entry alpha_instr_tbl_ext11[];
extern opcode_tab_entry alpha_instr_tbl_ext12[];
extern opcode_tab_entry alpha_instr_tbl_ext13[];
extern opcode_tab_entry alpha_instr_tbl_ext14[];
extern opcode_tab_entry alpha_instr_tbl_ext15[];
extern opcode_tab_entry alpha_instr_tbl_ext16[];
extern opcode_tab_entry alpha_instr_tbl_ext17[];
extern opcode_tab_entry alpha_instr_tbl_ext18[];
extern opcode_tab_entry alpha_instr_tbl_ext1a[];
extern opcode_tab_entry alpha_instr_tbl_ext1c[];
extern alpha_opcode_tab_entry alpha_instr_tbl[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext10[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext11[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext12[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext13[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext14[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext15[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext16[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext17[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext18[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext1a[];
extern alpha_opcode_tab_entry alpha_instr_tbl_ext1c[];

#define REG_ZERO 0x1f
#define REG_FLOAT 0x20
Expand Down
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