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Add more peripherals for the stm32f030 #6

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merged 20 commits into from
Dec 19, 2018
Merged

Add more peripherals for the stm32f030 #6

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b724b52
Add spi for stm32f030 (incomplete)
david-sawatzke Dec 16, 2018
66b869d
Add i2c for stm32f030 (incomplete)
david-sawatzke Dec 16, 2018
d059c11
Enable macro less implementations of multiple usarts
david-sawatzke Dec 18, 2018
a26e44c
Use macros for initalization code
david-sawatzke Dec 18, 2018
50f76b9
Remove duplicate features
david-sawatzke Dec 18, 2018
1c21cc7
Add some documentation to serial
david-sawatzke Dec 18, 2018
f3fe126
Enable gpiod, since stm32f0 crate was updated
david-sawatzke Dec 18, 2018
4d5f926
Add serial single pin traits and implement all af pins
david-sawatzke Dec 18, 2018
b8ec4e4
Enable usart6, since stm32f0 crate was updated
david-sawatzke Dec 18, 2018
e5f7a2c
Make USART pins macro more flexible
HarkonenBade Dec 18, 2018
0e03a32
Adjust note for confusing pin
david-sawatzke Dec 18, 2018
928fd64
Settle PB10
david-sawatzke Dec 18, 2018
f1f2b32
Implement single pin trait based AF for I2C
david-sawatzke Dec 19, 2018
527f182
Implement single pin trait based AF for SPI
david-sawatzke Dec 19, 2018
ad830af
Remove unecessary serial pin restriction
david-sawatzke Dec 19, 2018
14aab2a
Implement multiple spi instances (BROKEN)
david-sawatzke Dec 19, 2018
78b252a
Fix the rustc crash and other things
david-sawatzke Dec 19, 2018
a51bb0e
Add pins for SPI2
david-sawatzke Dec 19, 2018
2aa1d1b
Generalize i2c and port to i2c2
david-sawatzke Dec 19, 2018
5f7e6a6
Rework timers so there are no warnings
david-sawatzke Dec 19, 2018
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4 changes: 2 additions & 2 deletions Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -51,8 +51,8 @@ stm32f042 = ["stm32f0/stm32f0x2"]
stm32f030 = ["stm32f0/stm32f0x0"]
stm32f030x4 = ["stm32f030x6"]
stm32f030x6 = ["stm32f030"]
stm32f030x8 = ["stm32f030", "stm32f0/stm32f0x0"]
stm32f030xc = ["stm32f030", "stm32f0/stm32f0x0"]
stm32f030x8 = ["stm32f030"]
stm32f030xc = ["stm32f030"]
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Snuck in another unrelated change, eh? ;)

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It's technically not completely unrelated


[profile.dev]
debug = true
Expand Down
10 changes: 4 additions & 6 deletions src/gpio.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -564,12 +564,10 @@ gpio!(GPIOC, gpioc, iopcen, PC, [
PC15: (pb15, 15, Input<Floating>),
]);

// TODO Check if the bit is implemented yet
// In the device crate the iopden bit is missing, so it won't compile
// #[cfg(feature = "stm32f030")]
// gpio!(GPIOD, gpiod, iopden, PD, [
// PD2: (pd2, 2, Input<Floating>),
// ]);
#[cfg(feature = "stm32f030")]
gpio!(GPIOD, gpiod, iopden, PD, [
PD2: (pd2, 2, Input<Floating>),
]);

#[cfg(feature = "stm32f042")]
gpio!(GPIOF, gpiof, iopfen, PF, [
Expand Down
178 changes: 125 additions & 53 deletions src/i2c.rs
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Original file line number Diff line number Diff line change
@@ -1,66 +1,134 @@
#[cfg(feature = "stm32f042")]
use crate::stm32::{I2C1, RCC};
use core::ops::Deref;

use crate::stm32;
use embedded_hal::blocking::i2c::{Write, WriteRead};

use core::cmp;
#[cfg(feature = "stm32f042")]
use crate::gpio::gpioa::{PA10, PA11, PA12, PA9};
#[cfg(feature = "stm32f042")]
use crate::gpio::gpiob::{PB10, PB11, PB13, PB14, PB6, PB7, PB8, PB9};
#[cfg(feature = "stm32f042")]
use crate::gpio::gpiof::{PF0, PF1};
#[cfg(feature = "stm32f042")]
use crate::gpio::{Alternate, AF1, AF4, AF5};
use crate::gpio::*;
use crate::time::{KiloHertz, U32Ext};
use core::cmp;

/// I2C abstraction
pub struct I2c<I2C, PINS> {
pub struct I2c<I2C, SCLPIN, SDAPIN> {
i2c: I2C,
pins: PINS,
pins: (SCLPIN, SDAPIN),
}

pub trait Pins<I2c> {}

#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PA9<Alternate<AF4>>, PA10<Alternate<AF4>>) {}
#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PA11<Alternate<AF5>>, PA12<Alternate<AF5>>) {}
#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PB6<Alternate<AF1>>, PB7<Alternate<AF1>>) {}
#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PB8<Alternate<AF1>>, PB9<Alternate<AF1>>) {}
#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PB10<Alternate<AF1>>, PB11<Alternate<AF1>>) {}
#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PB13<Alternate<AF5>>, PB14<Alternate<AF5>>) {}
#[cfg(feature = "stm32f042")]
impl Pins<I2C1> for (PF1<Alternate<AF1>>, PF0<Alternate<AF1>>) {}
pub trait SclPin<I2C> {}
pub trait SdaPin<I2C> {}

macro_rules! i2c_pins {
($($I2C:ident => {
scl => [$($scl:ty),+ $(,)*],
sda => [$($sda:ty),+ $(,)*],
})+) => {
$(
$(
impl SclPin<stm32::$I2C> for $scl {}
)+
$(
impl SdaPin<stm32::$I2C> for $sda {}
)+
)+
}
}

#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
i2c_pins! {
I2C1 => {
scl => [gpioa::PA11<Alternate<AF5>>, gpiob::PB6<Alternate<AF1>>, gpiob::PB8<Alternate<AF1>>],
sda => [gpioa::PA12<Alternate<AF5>>, gpiob::PB7<Alternate<AF1>>, gpiob::PB9<Alternate<AF1>>],
}
}
#[cfg(any(
feature = "stm32f042",
feature = "stm32f030x6",
feature = "stm32f030xc"
))]
i2c_pins! {
I2C1 => {
scl => [gpioa::PA9<Alternate<AF4>>],
sda => [gpioa::PA10<Alternate<AF4>>],
}
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030x6"))]
i2c_pins! {
I2C1 => {
scl => [gpiob::PB10<Alternate<AF1>>],
sda => [gpiob::PB11<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030xc"))]
i2c_pins! {
I2C1 => {
scl => [gpiob::PB13<Alternate<AF5>>, gpiof::PF1<Alternate<AF1>>],
sda => [gpiob::PB14<Alternate<AF5>>, gpiof::PF0<Alternate<AF1>>],
}
}
#[cfg(any(feature = "stm32f030x8", feature = "stm32f030xc"))]
i2c_pins! {
I2C2 => {
scl => [gpiob::PB10<Alternate<AF1>>],
sda => [gpiob::PB11<Alternate<AF1>>],
}
}
#[cfg(feature = "stm32f030xc")]
i2c_pins! {
I2C2 => {
scl => [gpiob::PB13<Alternate<AF5>>],
sda => [gpiob::PB14<Alternate<AF5>>],
}
}

#[derive(Debug)]
pub enum Error {
OVERRUN,
NACK,
}

#[cfg(feature = "stm32f042")]
impl<PINS> I2c<I2C1, PINS> {
pub fn i2c1(i2c: I2C1, pins: PINS, speed: KiloHertz) -> Self
where
PINS: Pins<I2C1>,
{
// NOTE(unsafe) This executes only during initialisation
let rcc = unsafe { &(*RCC::ptr()) };

/* Enable clock for I2C1 */
rcc.apb1enr.modify(|_, w| w.i2c1en().set_bit());

/* Reset I2C1 */
rcc.apb1rstr.modify(|_, w| w.i2c1rst().set_bit());
rcc.apb1rstr.modify(|_, w| w.i2c1rst().clear_bit());
macro_rules! i2c {
($($I2C:ident: ($i2c:ident, $i2cXen:ident, $i2cXrst:ident, $apbenr:ident, $apbrstr:ident),)+) => {
$(
use crate::stm32::$I2C;
impl<SCLPIN, SDAPIN> I2c<$I2C, SCLPIN, SDAPIN> {
pub fn $i2c(i2c: $I2C, pins: (SCLPIN, SDAPIN), speed: KiloHertz) -> Self
where
SCLPIN: SclPin<$I2C>,
SDAPIN: SdaPin<$I2C>,
{
// NOTE(unsafe) This executes only during initialisation
let rcc = unsafe { &(*stm32::RCC::ptr()) };

/* Enable clock for I2C */
rcc.$apbenr.modify(|_, w| w.$i2cXen().set_bit());

/* Reset I2C */
rcc.$apbrstr.modify(|_, w| w.$i2cXrst().set_bit());
rcc.$apbrstr.modify(|_, w| w.$i2cXrst().clear_bit());
I2c { i2c, pins }.i2c_init(speed)
}
}
)+
}
}
#[cfg(any(feature = "stm32f042", feature = "stm32f030"))]
i2c! {
I2C1: (i2c1, i2c1en, i2c1rst, apb1enr, apb1rstr),
}
#[cfg(any(feature = "stm32f030xc", feature = "stm32f030xc"))]
i2c! {
I2C2: (i2c2, i2c2en, i2c2rst, apb1enr, apb1rstr),
}

// It's s needed for the impls, but rustc doesn't recognize that
#[allow(dead_code)]
type I2cRegisterBlock = stm32::i2c1::RegisterBlock;
impl<I2C, SCLPIN, SDAPIN> I2c<I2C, SCLPIN, SDAPIN>
where
I2C: Deref<Target = I2cRegisterBlock>,
{
fn i2c_init(self: Self, speed: KiloHertz) -> Self {
/* Make sure the I2C unit is disabled so we can configure it */
i2c.cr1.modify(|_, w| w.pe().clear_bit());
self.i2c.cr1.modify(|_, w| w.pe().clear_bit());

// Calculate settings for I2C speed modes
let presc;
Expand Down Expand Up @@ -88,7 +156,7 @@ impl<PINS> I2c<I2C1, PINS> {
}

/* Enable I2C signal generator, and configure I2C for 400KHz full speed */
i2c.timingr.write(|w| {
self.i2c.timingr.write(|w| {
w.presc()
.bits(presc)
.scldel()
Expand All @@ -102,12 +170,12 @@ impl<PINS> I2c<I2C1, PINS> {
});

/* Enable the I2C processing */
i2c.cr1.modify(|_, w| w.pe().set_bit());
self.i2c.cr1.modify(|_, w| w.pe().set_bit());

I2c { i2c, pins }
self
}

pub fn release(self) -> (I2C1, PINS) {
pub fn release(self) -> (I2C, (SCLPIN, SDAPIN)) {
(self.i2c, self.pins)
}

Expand Down Expand Up @@ -136,8 +204,10 @@ impl<PINS> I2c<I2C1, PINS> {
}
}

#[cfg(feature = "stm32f042")]
impl<PINS> WriteRead for I2c<I2C1, PINS> {
impl<I2C, SCLPIN, SDAPIN> WriteRead for I2c<I2C, SCLPIN, SDAPIN>
where
I2C: Deref<Target = I2cRegisterBlock>,
{
type Error = Error;

fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
Expand Down Expand Up @@ -214,8 +284,10 @@ impl<PINS> WriteRead for I2c<I2C1, PINS> {
}
}

#[cfg(feature = "stm32f042")]
impl<PINS> Write for I2c<I2C1, PINS> {
impl<I2C, SCLPIN, SDAPIN> Write for I2c<I2C, SCLPIN, SDAPIN>
where
I2C: Deref<Target = I2cRegisterBlock>,
{
type Error = Error;

fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
Expand Down
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