A small collection of tutorials and tools for ASIC design.
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Updated
May 16, 2017 - SystemVerilog
A small collection of tutorials and tools for ASIC design.
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Repository gathering basic modules for CDC purpose
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
Benchmark fo state-of-the-art Precision Scalable MAC Arrays (PSMAs)
Simple single-port AXI memory interface
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
Logic Analyzer IP Core
SystemVerilog Logger
Moore.io Demo Project
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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