SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

Various HDL (Verilog) IP Cores

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Custom chips reverse-engineered from silicon

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

IC implementation of Systolic Array for TPU

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

A simple Verilog SPI master / slave implementation featuring all 4 modes.

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …