cdsAsync: An Asynchronous VLSI Toolset & Schematic Library

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

"Design of ASIC" - appointment project

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

A tested & working VGA card capable of displaying graphics on CRT, LCD and LED monitors.

Verification of Digital Systems (EE382M)

Master thesis presents the elevator control algorithm and its implementation as an application-specific integrated circuit in the top-down technique.

Repository for my VLSI I final project. We build a naive ML processor in Verilog and simulated and synthesised it using Cadence Tools.

UCLA EE115C - Neural Spike Detector

8bit x 8bit Signed Wallace Tree Multiplier 600nm CMOS VLSI Design

Discover the 32-Bit RISC Processor Architecture based on MIPS, designed for efficient computing. This repository includes a comprehensive simulation and implementation guide, detailed documentation, and fully commented Verilog code, making it an invaluable resource for students and professionals interested in hardware design and computer architectu