Pipelined-Multiplier

Verilog code for a pipelined multiplier that produces a result every clock cycle

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
vpl_8b2to1mux_v.v		vpl_8b2to1mux_v.v
vpl_8badd_v.v		vpl_8badd_v.v
vpl_dff_v.v		vpl_dff_v.v
vpl_lab11_v.v		vpl_lab11_v.v
vpl_lab11_v_tb.v		vpl_lab11_v_tb.v
vpl_mplreg_v.v		vpl_mplreg_v.v
vpl_mreg_v.v		vpl_mreg_v.v
vpl_phreg_v.v		vpl_phreg_v.v

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