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Remove intended formfeeds.
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* lisp/progmodes/verilog-mode.el (verilog-auto-inst)
(verilog-auto-inst-param): Remove intended formfeeds.  Our ability to
detect unintended formfeeds elsewhere outweighs their limited utility
here.
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mattiase authored and wsnyder committed Mar 1, 2024
1 parent 6e056e2 commit 7448f97
Showing 1 changed file with 9 additions and 9 deletions.
18 changes: 9 additions & 9 deletions verilog-mode.el
Original file line number Diff line number Diff line change
Expand Up @@ -12526,7 +12526,7 @@ Typing \\[verilog-auto] will make this into:
endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

Unless you are instantiating a module multiple times, or the module is
Expand All @@ -12551,7 +12551,7 @@ Exceptions:
// Outputs
.o (o[31:0]));


Templates:

For multiple instantiations based upon a single template, create a
Expand Down Expand Up @@ -12622,7 +12622,7 @@ Templates:
.ptl_bus (ptl_busnew[3:0]),
....


Multiple Module Templates:

The same template lines can be applied to multiple modules with
Expand All @@ -12637,7 +12637,7 @@ Multiple Module Templates:
*/

Note there is only one AUTO_TEMPLATE opening parenthesis.

@ Templates:

It is common to instantiate a cell multiple times, so templates make it
Expand Down Expand Up @@ -12702,7 +12702,7 @@ Multiple Module Templates:
.ptl_mapvalidx (BAR_ptl_mapvalid),
.ptl_mapvalidp1x (ptl_mapvalid_BAR));


Regexp Templates:

A template entry of the form
Expand All @@ -12726,7 +12726,7 @@ Regexp Templates:
subscript:

.\\(.*\\)_l (\\1_[]),

Lisp Templates:

First any regular expression template is expanded.
Expand Down Expand Up @@ -12771,7 +12771,7 @@ Lisp Templates:
After the evaluation is completed, @ substitution and [] substitution
occur.


Ignoring Hookup:

AUTOWIRE and related AUTOs will read the signals created by a template.
Expand All @@ -12780,7 +12780,7 @@ Ignoring Hookup:

.pci_req_l (pci_req_not_to_wire), //AUTONOHOOKUP


For more information see the \\[verilog-faq] and forums at URL
`https://www.veripool.org'."
(save-excursion
Expand Down Expand Up @@ -12934,7 +12934,7 @@ Typing \\[verilog-auto] will make this into:
endmodule

Where the list of parameter connections come from the inst module.

Templates:

You can customize the parameter connections using AUTO_TEMPLATEs,
Expand Down

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