Skip to content
View vfinel's full-sized avatar

Block or report vfinel

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. nopywer nopywer Public

    Analyse power grid stuff from QGIS data

    Python 2

  2. axi axi Public

    Forked from skokvermon/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog

  3. common_verification common_verification Public

    Forked from skokvermon/common_verification

    SystemVerilog modules and classes commonly used for verification

    SystemVerilog

  4. common_cells common_cells Public

    Forked from skokvermon/common_cells

    Common SystemVerilog components

    SystemVerilog

  5. axi_mem_if axi_mem_if Public

    Forked from skokvermon/axi_mem_if

    Simple single-port AXI memory interface

    SystemVerilog

  6. fusesoc fusesoc Public

    Forked from skokvermon/fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    Python