A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

The UVM written in Python

Digital signal processing for neural time series.

A little bit about a linux kernel

Modern software development for embedded systems

Blackrock Microsystems Cerebus Link for Neural Signal Processing

A configurable RTL to bitstream FPGA toolchain

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Universal utility for programming FPGA

Programmer for the Lattice ECP5 series, making use of FTDI based adaptors

A modern hardware definition language and toolchain based on Python

PyTorch model to RTL flow for low latency inference

Flipper Zero firmware source code

SERV - The SErial RISC-V CPU