[LLVM][XTHeadVector] Implement intrinsics for vnsrl/vnsra. (llvm#57)

* [LLVM][XTHeadVector] Define intrinsics for vnsra/vnsrl.

* [LLVM][XTHeadVector] Define pseudos and pats for vnsrl/vnsra.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update Readme.

README.md

@@ -43,6 +43,7 @@ Any feature not listed below but present in the specification should be consider
       - (Done) `vsll.{vv,vx,vi}`
       - (Done) `vsrl.{vv,vx,vi}`
       - (Done) `vsra.{vv,vx,vi}`
+    - (Done) `12.6. Vector Narrowing Integer Right Shift Instructions`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -600,6 +600,18 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 4;
   }
 
+  // For destination vector type is the same as
+  // first source vector (with mask but no policy).
+  // The second source operand must match the destination type or be an XLen scalar.
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+  class XVBinaryABShiftMasked
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 4;
+  }
+
   multiclass XVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
@@ -614,6 +626,11 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : RISCVBinaryAAShiftUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVBinaryAAShiftMasked;
   }
+
+  multiclass XVBinaryABShift {
+    def "int_riscv_" # NAME : RISCVBinaryABShiftUnMasked;
+    def "int_riscv_" # NAME # "_mask" : XVBinaryABShiftMasked;
+  }
 }
 
 let TargetPrefix = "riscv" in {
@@ -648,6 +665,10 @@ let TargetPrefix = "riscv" in {
   defm th_vsll : XVBinaryAAShift;
   defm th_vsrl : XVBinaryAAShift;
   defm th_vsra : XVBinaryAAShift;
+
+  // 12.6. Vector Narrowing Integer Right Shift Instructions
+  defm th_vnsrl : XVBinaryABShift;
+  defm th_vnsra : XVBinaryABShift;
 } // TargetPrefix = "riscv"
 
 let TargetPrefix = "riscv" in {

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -1645,6 +1645,28 @@ multiclass XVPseudoBinaryW_WX<LMULInfo m> {
   defm _WX : XVPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
 }
 
+// In RVV 1.0 `@earlyclobber` is used here to prevent the source and destination
+// from overlapping. The case where LMUL <= 1 is excluded because of the
+// exception from the 1.0 spec:
+// "The destination EEW is smaller than the source EEW and the overlap is in the
+//  lowest-numbered part of the source register group."
+// However, the 0.7 spec is unclear about the source-destination overlapping of
+// narrowing instructions like vnsrl/vnsra. Here we simply follow the 1.0 spec.
+multiclass XVPseudoBinaryVNSHT_VV<LMULInfo m> {
+  defm _VV : XVPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
+                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
+}
+
+multiclass XVPseudoBinaryVNSHT_VX<LMULInfo m> {
+  defm _VX : XVPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
+                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
+}
+
+multiclass XVPseudoBinaryVNSHT_VI<LMULInfo m> {
+  defm _VI : XVPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
+                            !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
+}
+
 multiclass XVPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxListXTHeadV in {
     defvar mx = m.MX;
@@ -1807,6 +1829,24 @@ multiclass XVPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
   }
 }
 
+multiclass XVPseudoVNSHT_VV_VX_VI {
+  foreach m = MxListWXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVNShiftV_MX = !cast<SchedWrite>("WriteVNShiftV_" # mx);
+    defvar WriteVNShiftX_MX = !cast<SchedWrite>("WriteVNShiftX_" # mx);
+    defvar WriteVNShiftI_MX = !cast<SchedWrite>("WriteVNShiftI_" # mx);
+    defvar ReadVNShiftV_MX = !cast<SchedRead>("ReadVNShiftV_" # mx);
+    defvar ReadVNShiftX_MX = !cast<SchedRead>("ReadVNShiftX_" # mx);
+
+    defm "" : XVPseudoBinaryVNSHT_VV<m>,
+              Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryVNSHT_VX<m>,
+              Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryVNSHT_VI<m>,
+              Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -2053,6 +2093,49 @@ multiclass XVPatBinaryV_IM<string intrinsic, string instruction,
                              vti.RegClass, simm5>;
 }
 
+multiclass XVPatBinaryVNSHT_VV<string intrinsic, string instruction,
+                               list<VTypeInfoToWide> vtilist> {
+  foreach VtiToWti = vtilist in {
+    defvar Vti = VtiToWti.Vti;
+    defvar Wti = VtiToWti.Wti;
+    let Predicates = !listconcat(GetXVTypePredicates<Vti>.Predicates,
+                                 GetXVTypePredicates<Wti>.Predicates) in
+    defm : XVPatBinary<intrinsic, instruction # "_VV_" # Vti.LMul.MX,
+                       Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
+                       Vti.Log2SEW, Vti.RegClass,
+                       Wti.RegClass, Vti.RegClass>;
+  }
+}
+
+multiclass XVPatBinaryVNSHT_VX<string intrinsic, string instruction,
+                               list<VTypeInfoToWide> vtilist> {
+  foreach VtiToWti = vtilist in {
+    defvar Vti = VtiToWti.Vti;
+    defvar Wti = VtiToWti.Wti;
+    defvar kind = "V"#Vti.ScalarSuffix;
+    let Predicates = !listconcat(GetXVTypePredicates<Vti>.Predicates,
+                                 GetXVTypePredicates<Wti>.Predicates) in
+    defm : XVPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
+                       Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
+                       Vti.Log2SEW, Vti.RegClass,
+                       Wti.RegClass, Vti.ScalarRegClass>;
+  }
+}
+
+multiclass XVPatBinaryVNSHT_VI<string intrinsic, string instruction,
+                               list<VTypeInfoToWide> vtilist> {
+  foreach VtiToWti = vtilist in {
+    defvar Vti = VtiToWti.Vti;
+    defvar Wti = VtiToWti.Wti;
+    let Predicates = !listconcat(GetXVTypePredicates<Vti>.Predicates,
+                                 GetXVTypePredicates<Wti>.Predicates) in
+    defm : XVPatBinary<intrinsic, instruction # "_VI_" # Vti.LMul.MX,
+                       Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
+                       Vti.Log2SEW, Vti.RegClass,
+                       Wti.RegClass, uimm5>;
+  }
+}
+
 multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
                                  list<VTypeInfo> vtilist, Operand ImmType = simm5>
     : XVPatBinaryV_VV<intrinsic, instruction, vtilist>,
@@ -2097,6 +2180,12 @@ multiclass XVPatBinaryM_VM_XM<string intrinsic, string instruction>
     : XVPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,
       XVPatBinaryV_XM<intrinsic, instruction, CarryOut=1>;
 
+multiclass XVPatBinaryVNSHT_VV_VX_VI<string intrinsic, string instruction,
+                                     list<VTypeInfoToWide> vtilist>
+    : XVPatBinaryVNSHT_VV<intrinsic, instruction, vtilist>,
+      XVPatBinaryVNSHT_VX<intrinsic, instruction, vtilist>,
+      XVPatBinaryVNSHT_VI<intrinsic, instruction, vtilist>;
+
 //===----------------------------------------------------------------------===//
 // 12.1. Vector Single-Width Saturating Add and Subtract
 //===----------------------------------------------------------------------===//
@@ -2267,6 +2356,19 @@ let Predicates = [HasVendorXTHeadV] in {
   }
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 12.6. Vector Narrowing Integer Right Shift Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VNSRL : XVPseudoVNSHT_VV_VX_VI;
+  defm PseudoTH_VNSRA : XVPseudoVNSHT_VV_VX_VI;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryVNSHT_VV_VX_VI<"int_riscv_th_vnsrl", "PseudoTH_VNSRL", AllWidenableIntXVectors>;
+  defm : XVPatBinaryVNSHT_VV_VX_VI<"int_riscv_th_vnsra", "PseudoTH_VNSRA", AllWidenableIntXVectors>;
+}
+
 //===----------------------------------------------------------------------===//
 // 12.14. Vector Integer Merge and Move Instructions
 //===----------------------------------------------------------------------===//