* updated with corrections in gpio irq.

* usticker file updated with latest source.

libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/gpio_irq_api.c

@@ -22,13 +22,15 @@
 
 #define IRQ_RISE_POSITION   1
 #define IRQ_FALL_POSITION   2
-#define CHANNEL_NUM         32
-#define MAX_PORT_NUM        2
+#define CHANNEL_NUM         48
+#define MAX_PINS_IN_PORT    32
 
 static uint32_t channel_ids[CHANNEL_NUM] = {0};
 static gpio_irq_handler irq_handler;
 extern uint8_t ioinit;
 
+static IRQn_Type pin_to_irq (uint32_t pin);
+
 void gpio_irq_common_handler(uint32_t port_id)
 {
     uint32_t i = 0, status = 0, mask = 0, temp = 0;
@@ -39,7 +41,7 @@ void gpio_irq_common_handler(uint32_t port_id)
     status = pio_base->PIO_ISR;
     status = status & mask;
 
-    for (i = 0; i < 32 ; i++) {
+    for (i = 0; i < MAX_PINS_IN_PORT ; i++) {
         temp = (1 << i );
         if (status & temp ) {
             if((pio_base->PIO_PDSR) & temp) {
@@ -48,7 +50,7 @@ void gpio_irq_common_handler(uint32_t port_id)
                 event = IRQ_FALL;
             }
             if(irq_handler) {
-                irq_handler(channel_ids[i], event);
+                irq_handler(channel_ids[(port_id * 32) + i], event);
             }
         }
     }
@@ -78,11 +80,10 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     uint32_t port_id;
     uint32_t vector = 0;
     uint8_t int_channel = 0;
-    uint32_t dummyread = 0;
     Pio* pio_base;
 
     irq_handler = handler;  // assuming the usage of these apis in mbed layer only
-    int_channel = pin % 32; /*to get the channel to be used*/
+    int_channel = ((pin / 32) * 32)  + (pin % 32); /*to get the channel to be used*/
     channel_ids[int_channel] = id;
     obj->pin = pin;
     port_id = ioport_pin_to_port_id(pin);
@@ -91,18 +92,18 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     ioport_set_pin_dir(pin, IOPORT_DIR_INPUT); /*Pin to be configured input for GPIO Interrupt*/
     ioport_set_pin_mode(pin, IOPORT_MODE_PULLUP);
 
+    irq_n = pin_to_irq(pin);
+
     switch (port_id) {
             /*only 2 ports for SAMG55*/ /*Setting up the vectors*/
         case IOPORT_PIOA :
-            irq_n = PIOA_IRQn;
             vector = (uint32_t)gpio_irq_porta;
             break;
         case IOPORT_PIOB :
-            irq_n = PIOB_IRQn;
             vector = (uint32_t)gpio_irq_portb;
             break;
     }
-    dummyread = pio_base->PIO_ISR; /*To read and clear status register*/
+    pio_base->PIO_ISR; /*To read and clear status register*/
     NVIC_SetVector(irq_n, vector);
     NVIC_EnableIRQ(irq_n);
 
@@ -112,7 +113,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
 void gpio_irq_free(gpio_irq_t *obj)
 {
     MBED_ASSERT(obj);
-    channel_ids[(obj->pin) % 32] = 0;
+    channel_ids[((obj->pin / 32) * 32)  + (obj->pin % 32)] = 0;
 }
 
 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
@@ -137,7 +138,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
             obj->irqmask &= ~IRQ_FALL_POSITION;
         }
     }
-
+    pio_base->PIO_ISR; /*To read and clear status register*/
     if (obj->irqmask == (IRQ_RISE_POSITION | IRQ_FALL_POSITION)) { /*both edge detection*/
         pio_base->PIO_AIMDR = mask;
         pio_base->PIO_IER = mask;

libraries/mbed/targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c

@@ -23,17 +23,51 @@
 
 static uint8_t us_ticker_inited = 0;
 extern uint8_t g_sys_init;
+uint16_t us_ticker_16bit_counter;
+uint16_t us_ticker_interrupt_counter;
+uint16_t us_ticker_interrupt_offset;
 
-#define TICKER_COUNTER_CLK      ID_TC0
-#define TICKER_COUNTER_uS       TC0
-#define TICKER_COUNTER_CHANNEL  0
-#define TICKER_COUNTER_IRQn     TC0_IRQn
-#define TICKER_COUNTER_Handlr   TC0_Handler
+#define TICKER_COUNTER_uS        TC0
 
-void TICKER_COUNTER_Handlr(void)
+#define TICKER_COUNTER_CLK0      ID_TC0
+#define TICKER_COUNTER_CLK1      ID_TC1
+
+#define TICKER_COUNTER_CHANNEL0  0
+#define TICKER_COUNTER_IRQn0     TC0_IRQn
+#define TICKER_COUNTER_Handlr0   TC0_Handler
+
+#define TICKER_COUNTER_CHANNEL1  1
+#define TICKER_COUNTER_IRQn1     TC1_IRQn
+#define TICKER_COUNTER_Handlr1   TC1_Handler
+
+#define OVERFLOW_16bit_VALUE    0xFFFF
+
+
+void TICKER_COUNTER_Handlr1(void)
 {
-    if ((tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL) & TC_IER_CPAS) == TC_IER_CPAS) {
-        us_ticker_irq_handler();
+    uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+    uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+
+    if (((status & interrupmask)  & TC_IER_CPCS)) {
+        if(us_ticker_interrupt_counter) {
+            us_ticker_interrupt_counter--;
+        } else {
+            if(us_ticker_interrupt_offset) {
+                tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)us_ticker_interrupt_offset);
+                us_ticker_interrupt_offset=0;
+            } else
+                us_ticker_irq_handler();
+        }
+    }
+}
+
+void TICKER_COUNTER_Handlr0(void)
+{
+    uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+    uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+
+    if (((status & interrupmask)  & TC_IER_COVFS)) {
+        us_ticker_16bit_counter++;
     }
 }
 
@@ -42,13 +76,18 @@ void us_ticker_init(void)
     if (us_ticker_inited) return;
     us_ticker_inited = 1;
 
+    us_ticker_16bit_counter=0;
+    us_ticker_interrupt_counter=0;
+    us_ticker_interrupt_offset=0;
+
     if (g_sys_init == 0) {
         sysclk_init();
         g_sys_init = 1;
     }
 
     /* Configure the PMC to enable the TC module. */
-    sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK);
+    sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK0);
+    sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK1);
 
 #if SAMG55
     /* Enable PCK output */
@@ -57,20 +96,29 @@ void us_ticker_init(void)
     pmc_enable_pck(PMC_PCK_3);
 #endif
 
-    /* Init TC to waveform mode. */
-    tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL,
-            TC_CMR_TCCLKS_TIMER_CLOCK4
-           );
+    /* Init TC to Counter mode. */
+    tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_CMR_TCCLKS_TIMER_CLOCK4);
+    tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_CMR_TCCLKS_TIMER_CLOCK4);
+
+    NVIC_DisableIRQ(TICKER_COUNTER_IRQn0);
+    NVIC_SetVector(TICKER_COUNTER_IRQn0, (uint32_t)TICKER_COUNTER_Handlr0);
+
+    tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_IER_COVFS);
+
+    NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn0);
+    NVIC_SetPriority(TICKER_COUNTER_IRQn0, 0);
+    NVIC_EnableIRQ(TICKER_COUNTER_IRQn0);
 
-    tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL);
+    tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
 }
 
+
 uint32_t us_ticker_read()
 {
     if (!us_ticker_inited)
         us_ticker_init();
-
-    return tc_read_cv(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL);
+    uint32_t counter_value=tc_read_cv(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0);
+    return counter_value+(OVERFLOW_16bit_VALUE*us_ticker_16bit_counter);
 }
 
 void us_ticker_set_interrupt(timestamp_t timestamp)
@@ -86,27 +134,39 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
         return;
     }
 
-    NVIC_DisableIRQ(TICKER_COUNTER_IRQn);
-    NVIC_SetVector(TICKER_COUNTER_IRQn, (uint32_t)TICKER_COUNTER_Handlr);
+    uint16_t interruptat=0;
 
-    tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL, TC_IER_CPAS);
-    tc_write_ra(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL, (uint32_t)timestamp);
+    if(delta > OVERFLOW_16bit_VALUE) {
+        us_ticker_interrupt_counter= delta/OVERFLOW_16bit_VALUE;
+        us_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE;
+        interruptat=OVERFLOW_16bit_VALUE;
+    } else {
+        us_ticker_interrupt_counter=0;
+        us_ticker_interrupt_offset=0;
+        interruptat=delta;
+    }
 
-    NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn);
-    NVIC_SetPriority(TICKER_COUNTER_IRQn, 0);
-    NVIC_EnableIRQ(TICKER_COUNTER_IRQn);
+    NVIC_DisableIRQ(TICKER_COUNTER_IRQn1);
+    NVIC_SetVector(TICKER_COUNTER_IRQn1, (uint32_t)TICKER_COUNTER_Handlr1);
 
+    tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)interruptat);
+    tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS );
 
+    NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
+    NVIC_SetPriority(TICKER_COUNTER_IRQn1, 0);
+    NVIC_EnableIRQ(TICKER_COUNTER_IRQn1);
+
+    tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
 }
 
 void us_ticker_disable_interrupt(void)
 {
-    tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL);
-    tc_disable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL, TC_IER_CPAS);
-    NVIC_DisableIRQ(TICKER_COUNTER_IRQn);
+    tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1);
+    tc_disable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS);
+    NVIC_DisableIRQ(TICKER_COUNTER_IRQn1);
 }
 
 void us_ticker_clear_interrupt(void)
 {
-    NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn);
-}
+    NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1);
+}