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Added 'A' Support
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Bohan Hu committed Oct 24, 2020
1 parent 091ae64 commit 0f53ca4
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Showing 7 changed files with 301 additions and 145 deletions.
149 changes: 83 additions & 66 deletions src/main/scala/common/Consts.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,111 +12,128 @@ package common {
val N = false.B

// PC Select Signal
val PC_4 = 0.asUInt(2.W) // PC + 4
val PC_BRJMP = 1.asUInt(2.W) // brjmp_target
val PC_JALR = 2.asUInt(2.W) // jump_reg_target
val PC_EXC = 3.asUInt(2.W) // exception
val PC_4 = 0.asUInt(2.W) // PC + 4
val PC_BRJMP = 1.asUInt(2.W) // brjmp_target
val PC_JALR = 2.asUInt(2.W) // jump_reg_target
val PC_EXC = 3.asUInt(2.W) // exception

// Branch Type
val BR_N = 0.asUInt(4.W) // Next
val BR_NE = 1.asUInt(4.W) // Branch on NotEqual
val BR_EQ = 2.asUInt(4.W) // Branch on Equal
val BR_GE = 3.asUInt(4.W) // Branch on Greater/Equal
val BR_GEU = 4.asUInt(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.asUInt(4.W) // Branch on Less Than
val BR_LTU = 6.asUInt(4.W) // Branch on Less Than Unsigned
val BR_J = 7.asUInt(4.W) // Jump
val BR_JR = 8.asUInt(4.W) // Jump Register
val BR_N = 0.asUInt(4.W) // Next
val BR_NE = 1.asUInt(4.W) // Branch on NotEqual
val BR_EQ = 2.asUInt(4.W) // Branch on Equal
val BR_GE = 3.asUInt(4.W) // Branch on Greater/Equal
val BR_GEU = 4.asUInt(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.asUInt(4.W) // Branch on Less Than
val BR_LTU = 6.asUInt(4.W) // Branch on Less Than Unsigned
val BR_J = 7.asUInt(4.W) // Jump
val BR_JR = 8.asUInt(4.W) // Jump Register

// Operand #1 Select Signal
// Operand #1 could be RS1, PC.
val OP1_RS1 = 0.asUInt(2.W) // Register Source #1
val OP1_PC = 1.asUInt(2.W) // PC
val OP1_X = 0.asUInt(2.W) // Don't care
val OP1_RS1 = 0.asUInt(2.W) // Register Source #1
val OP1_PC = 1.asUInt(2.W) // PC
val OP1_X = 0.asUInt(2.W) // Don't care

// Operand #2 Select Signal
// Operand #2 could be RS2, sign-extended or zero-extended(for CSRs) immediate
val OP2_RS2 = 0.asUInt(3.W) // Register Source #2
val IMM_ITYPE = 1.asUInt(3.W) // I-type
val IMM_STYPE = 2.asUInt(3.W) // S-type
val IMM_BTYPE = 3.asUInt(3.W) // B-type
val IMM_UTYPE = 4.asUInt(3.W) // U-type
val IMM_JTYPE = 5.asUInt(3.W) // J-type
val IMM_ZEXT = 6.asUInt(3.W) // Zero-extended Immediate from RS1 field, for use by CSRI instructions
val OP2_X = 0.asUInt(3.W)
val OP2_RS2 = 0.asUInt(3.W) // Register Source #2
val IMM_ITYPE = 1.asUInt(3.W) // I-type
val IMM_STYPE = 2.asUInt(3.W) // S-type
val IMM_BTYPE = 3.asUInt(3.W) // B-type
val IMM_UTYPE = 4.asUInt(3.W) // U-type
val IMM_JTYPE = 5.asUInt(3.W) // J-type
val IMM_ZEXT = 6.asUInt(3.W) // Zero-extended Immediate from RS1 field, for use by CSRI instructions
val IMM_ZERO = 7.asUInt(3.W) // Zero-extended Immediate from RS1 field, for use by CSRI instructions
val OP2_X = 0.asUInt(3.W)

// ALU Operation Signal
val ALU_ADD = 0.asUInt(4.W)
val ALU_SUB = 1.asUInt(4.W)
val ALU_SLL = 2.asUInt(4.W)
val ALU_SRL = 3.asUInt(4.W)
val ALU_SRA = 4.asUInt(4.W)
val ALU_AND = 5.asUInt(4.W)
val ALU_OR = 6.asUInt(4.W)
val ALU_XOR = 7.asUInt(4.W)
val ALU_SLT = 8.asUInt(4.W)
val ALU_SLTU = 9.asUInt(4.W)
val ALU_ADD = 0.asUInt(4.W)
val ALU_SUB = 1.asUInt(4.W)
val ALU_SLL = 2.asUInt(4.W)
val ALU_SRL = 3.asUInt(4.W)
val ALU_SRA = 4.asUInt(4.W)
val ALU_AND = 5.asUInt(4.W)
val ALU_OR = 6.asUInt(4.W)
val ALU_XOR = 7.asUInt(4.W)
val ALU_SLT = 8.asUInt(4.W)
val ALU_SLTU = 9.asUInt(4.W)
val ALU_COPY_1 = 10.asUInt(4.W)
val ALU_COPY_2 = 11.asUInt(4.W)
val ALU_X = 0.asUInt(4.W)
val ALU_X = 0.asUInt(4.W)

val LSU_X = 0.asUInt(4.W)
val LSU_LOAD = 1.asUInt(4.W)
val LSU_STORE = 2.asUInt(4.W)
val LSU_LR = 3.asUInt(4.W)
val LSU_SC = 4.asUInt(4.W)
val LSU_ASWAP = 5.asUInt(4.W)
val LSU_AADD = 6.asUInt(4.W)
val LSU_AXOR = 7.asUInt(4.W)
val LSU_AAND = 8.asUInt(4.W)
val LSU_AOR = 9.asUInt(4.W)
val LSU_AMIN = 10.asUInt(4.W)
val LSU_AMAX = 11.asUInt(4.W)
val LSU_AMINU = 12.asUInt(4.W)
val LSU_AMAXU = 13.asUInt(4.W)

// ALU Type
val OP_ARITH = 0.asUInt(3.W)
val OP_ARITH = 0.asUInt(3.W)
val OP_COMPARE = 1.asUInt(3.W)
val OP_LOGIC = 2.asUInt(3.W)
val OP_SHIFT = 3.asUInt(3.W)
val OP_COPY = 4.asUInt(3.W)
val OP_BR = 5.asUInt(3.W)
val OP_LOGIC = 2.asUInt(3.W)
val OP_SHIFT = 3.asUInt(3.W)
val OP_COPY = 4.asUInt(3.W)
val OP_BR = 5.asUInt(3.W)

// Writeback Select Signal
val WB_X = 0.asUInt(2.W)
val WB_X = 0.asUInt(2.W)
val WB_ALU = 0.asUInt(2.W)
val WB_MEM = 1.asUInt(2.W)
val WB_PC4 = 2.asUInt(2.W)
val WB_CSR = 3.asUInt(2.W)

// Mem Op
val MEM_NOP = 0.asUInt(2.W)
val MEM_READ = 1.asUInt(2.W)
val MEM_NOP = 0.asUInt(2.W)
val MEM_READ = 1.asUInt(2.W)
val MEM_WRITE = 2.asUInt(2.W)
val MEM_AMO = 3.asUInt(2.W)

// Mem Size and sign
val SZ_X = 0.asUInt(3.W)
val SZ_W = 0.asUInt(3.W)
val SZ_B = 1.asUInt(3.W)
val SZ_H = 2.asUInt(3.W)
val SZ_X = 0.asUInt(3.W)
val SZ_W = 0.asUInt(3.W)
val SZ_B = 1.asUInt(3.W)
val SZ_H = 2.asUInt(3.W)
val SZ_HU = 3.asUInt(3.W)
val SZ_BU = 4.asUInt(3.W)
val SZ_D = 5.asUInt(3.W)
val SZ_D = 5.asUInt(3.W)
val SZ_WU = 6.asUInt(3.W)

val CSR_X = 0.asUInt(3.W)
val CSR_W = 1.asUInt(3.W)
val CSR_S = 2.asUInt(3.W)
val CSR_C = 3.asUInt(3.W)
val CSR_X = 0.asUInt(3.W)
val CSR_W = 1.asUInt(3.W)
val CSR_S = 2.asUInt(3.W)
val CSR_C = 3.asUInt(3.W)
val CSR_SI = 4.asUInt(3.W)
val CSR_CI = 5.asUInt(3.W)
val CSR_I = 6.asUInt(3.W) // Trp
val CSR_I = 6.asUInt(3.W) // Trp

val FU_ALU = 0.asUInt(2.W)
val FU_LSU = 1.asUInt(2.W)
val FU_MUL = 2.asUInt(2.W)
val FU_DIV = 3.asUInt(2.W)

val MDU_MUL = 0.asUInt(4.W)
val MDU_MULH = 1.asUInt(4.W)
val MDU_MULHS = 2.asUInt(4.W)
val MDU_MUL = 0.asUInt(4.W)
val MDU_MULH = 1.asUInt(4.W)
val MDU_MULHS = 2.asUInt(4.W)
val MDU_MULHSU = 3.asUInt(4.W)
val MDU_MULHU = 4.asUInt(4.W)
val MDU_MULW = 5.asUInt(4.W)
val MDU_DIV = 6.asUInt(4.W)
val MDU_DIVU = 7.asUInt(4.W)
val MDU_REM = 8.asUInt(4.W)
val MDU_REMU = 9.asUInt(4.W)
val MDU_DIVW = 10.asUInt(4.W)
val MDU_DIVUW = 11.asUInt(4.W)
val MDU_REMW = 12.asUInt(4.W)
val MDU_REMUW = 13.asUInt(4.W)
val MDU_MULHU = 4.asUInt(4.W)
val MDU_MULW = 5.asUInt(4.W)
val MDU_DIV = 6.asUInt(4.W)
val MDU_DIVU = 7.asUInt(4.W)
val MDU_REM = 8.asUInt(4.W)
val MDU_REMU = 9.asUInt(4.W)
val MDU_DIVW = 10.asUInt(4.W)
val MDU_DIVUW = 11.asUInt(4.W)
val MDU_REMW = 12.asUInt(4.W)
val MDU_REMUW = 13.asUInt(4.W)
}

}
27 changes: 18 additions & 9 deletions src/main/scala/common/Instructions.scala
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Expand Up @@ -105,15 +105,24 @@ object Instructions {
val SC_D = BitPat("b00011_??_?????_?????_011_?????_0101111")
val LR_W = BitPat("b00010_??_00000_?????_010_?????_0101111")
val SC_W = BitPat("b00011_??_?????_?????_010_?????_0101111")
val AMOSWAP = BitPat("b00001_??_?????_?????_01?_?????_0101111")
val AMOADD = BitPat("b00000_??_?????_?????_01?_?????_0101111")
val AMOXOR = BitPat("b00100_??_?????_?????_01?_?????_0101111")
val AMOAND = BitPat("b01100_??_?????_?????_01?_?????_0101111")
val AMOOR = BitPat("b01000_??_?????_?????_01?_?????_0101111")
val AMOMIN = BitPat("b10000_??_?????_?????_01?_?????_0101111")
val AMOMAX = BitPat("b10100_??_?????_?????_01?_?????_0101111")
val AMOMINU = BitPat("b11000_??_?????_?????_01?_?????_0101111")
val AMOMAXU = BitPat("b11100_??_?????_?????_01?_?????_0101111")
val AMOSWAP_D = BitPat("b00001_??_?????_?????_011_?????_0101111")
val AMOADD_D = BitPat("b00000_??_?????_?????_011_?????_0101111")
val AMOXOR_D = BitPat("b00100_??_?????_?????_011_?????_0101111")
val AMOAND_D = BitPat("b01100_??_?????_?????_011_?????_0101111")
val AMOOR_D = BitPat("b01000_??_?????_?????_011_?????_0101111")
val AMOMIN_D = BitPat("b10000_??_?????_?????_011_?????_0101111")
val AMOMAX_D = BitPat("b10100_??_?????_?????_011_?????_0101111")
val AMOMINU_D = BitPat("b11000_??_?????_?????_011_?????_0101111")
val AMOMAXU_D = BitPat("b11100_??_?????_?????_011_?????_0101111")
val AMOSWAP_W = BitPat("b00001_??_?????_?????_010_?????_0101111")
val AMOADD_W = BitPat("b00000_??_?????_?????_010_?????_0101111")
val AMOXOR_W = BitPat("b00100_??_?????_?????_010_?????_0101111")
val AMOAND_W = BitPat("b01100_??_?????_?????_010_?????_0101111")
val AMOOR_W = BitPat("b01000_??_?????_?????_010_?????_0101111")
val AMOMIN_W = BitPat("b10000_??_?????_?????_010_?????_0101111")
val AMOMAX_W = BitPat("b10100_??_?????_?????_010_?????_0101111")
val AMOMINU_W = BitPat("b11000_??_?????_?????_010_?????_0101111")
val AMOMAXU_W = BitPat("b11100_??_?????_?????_010_?????_0101111")

}

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9 changes: 6 additions & 3 deletions src/main/scala/common/ram.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -65,19 +65,22 @@ class SyncReadWriteMem extends Module {
ram.io.clk := io.clk
// io.data_valid := RegNext(!io.reset)
val ack = Reg(Bool())

io.mem2dmem.memWrDone := true.B
val isMMIO = MMIO.inMMIORange(io.mem2dmem.memAddr)
// Fake UART
when(ack){
ack := false.B
}.elsewhen (io.mem2dmem.memRreq && !ack) {
ack := true.B
}.otherwise {
ack := false.B
}
ram.io.rIdx := Mux(io.mem2dmem.memAddr(63, 3) < 16777216.U, io.mem2dmem.memAddr(63, 3), 0.U)
ram.io.rIdx := Mux(io.mem2dmem.memAddr(63, 3) < 16777216.U & !isMMIO, io.mem2dmem.memAddr(63, 3), 0.U)
io.mem2dmem.memRdata := ram.io.rdata
ram.io.wIdx := Mux(io.mem2dmem.memAddr(63, 3) < 16777216.U, io.mem2dmem.memAddr(63, 3), 0.U)
ram.io.wIdx := Mux(io.mem2dmem.memAddr(63, 3) < 16777216.U & !isMMIO, io.mem2dmem.memAddr(63, 3), 0.U)
ram.io.wdata := io.mem2dmem.memWdata
ram.io.wmask := io.mem2dmem.memWmask
ram.io.wen := io.mem2dmem.memWen
io.mem2dmem.memRvalid := ack

}
2 changes: 1 addition & 1 deletion src/main/scala/core/csrFile.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -617,7 +617,7 @@ class CSRFile extends Module {
// ================== Exception Handler Entry Ends ===================

// Decide whether to enable the Sv39
io.csrMMU.enableSv39 := (privMode =/= M || satp(63, 60) === 8.U)
io.csrMMU.enableSv39 := (privMode =/= M && satp(63, 60) === 8.U)
io.csrMMU.asid := satp(59,44)
io.csrMMU.mxr := mstatus.asTypeOf(new mstatus).MXR
io.csrMMU.sum := mstatus.asTypeOf(new mstatus).SUM
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50 changes: 37 additions & 13 deletions src/main/scala/core/decode.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -51,17 +51,39 @@ class Decode extends Module {
val decodeops =
Array(/* val | BR | op1 | op2 | R1 | R2 | FU | FU | ALU is | wb | rf | is | mem | mask | csr | fence.i */
/* inst | type | sel | sel | ren | ren | op | TYPE | WordOp | sel | wen | mem | op | type | cmd | */
LD -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_D, CSR_X, N),
LW -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_W, CSR_X, N),
LWU -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_WU, CSR_X, N),
LB -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_B, CSR_X, N),
LBU -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_BU, CSR_X, N),
LH -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_H, CSR_X, N),
LHU -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, ALU_ADD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_HU, CSR_X, N),
SD -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, ALU_ADD, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_D, CSR_X, N),
SW -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, ALU_ADD, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_W, CSR_X, N),
SB -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, ALU_ADD, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_B, CSR_X, N),
SH -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, ALU_ADD, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_H, CSR_X, N),
LD -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_D, CSR_X, N),
LW -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_W, CSR_X, N),
LWU -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_WU, CSR_X, N),
LB -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_B, CSR_X, N),
LBU -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_BU, CSR_X, N),
LH -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_H, CSR_X, N),
LHU -> List(Y, BR_N, OP1_RS1, IMM_ITYPE, Y, N, LSU_LOAD, FU_LSU, N, WB_MEM, Y, Y, MEM_READ, SZ_HU, CSR_X, N),
SD -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, LSU_STORE, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_D, CSR_X, N),
SW -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, LSU_STORE, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_W, CSR_X, N),
SB -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, LSU_STORE, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_B, CSR_X, N),
SH -> List(Y, BR_N, OP1_RS1, IMM_STYPE, Y, Y, LSU_STORE, FU_LSU, N, WB_X, N, Y, MEM_WRITE, SZ_H, CSR_X, N),
LR_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, N, LSU_LR, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
SC_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_SC, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
LR_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, N, LSU_LR, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
SC_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_SC, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOSWAP_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_ASWAP, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOADD_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AADD, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOXOR_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AXOR, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOAND_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AAND, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOOR_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AOR, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOMIN_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMIN, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOMAX_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMAX, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOMINU_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMINU, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOMAXU_D -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMAXU, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_D, CSR_X, N),
AMOSWAP_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_ASWAP, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOADD_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AADD, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOXOR_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AXOR, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOAND_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AAND, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOOR_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AOR, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOMIN_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMIN, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOMAX_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMAX, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOMINU_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMINU, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
AMOMAXU_W -> List(Y, BR_N, OP1_RS1, IMM_ZERO, Y, Y, LSU_AMAXU, FU_LSU, N, WB_MEM, Y, Y, MEM_AMO, SZ_W, CSR_X, N),
// IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII_I
AUIPC -> List(Y, BR_N, OP1_PC, IMM_UTYPE, N, N, ALU_ADD, FU_ALU, N, WB_ALU, Y, N, MEM_NOP, SZ_X, CSR_X, N),
LUI -> List(Y, BR_N, OP1_X, IMM_UTYPE, N, N, ALU_COPY_2, FU_ALU, N, WB_ALU, Y, N, MEM_NOP, SZ_X, CSR_X, N),
Expand Down Expand Up @@ -135,8 +157,9 @@ class Decode extends Module {

FENCE_I -> List(Y, BR_N, OP1_X, OP2_X, N, N, ALU_X, FU_ALU, N, WB_X, N, N, MEM_NOP, SZ_X, CSR_X, Y),
// kill pipeline and refetch instructions since the pipeline will be holding stall instructions.
FENCE -> List(Y, BR_N, OP1_X, OP2_X, N, N, ALU_X, FU_ALU, N, WB_X, N, Y, MEM_NOP, SZ_X, CSR_X, N)
FENCE -> List(Y, BR_N, OP1_X, OP2_X, N, N, ALU_X, FU_ALU, N, WB_X, N, Y, MEM_NOP, SZ_X, CSR_X, N),
// we are already sequentially consistent, so no need to honor the fence instruction
SFENCE_VMA -> List(Y, BR_N, OP1_X, OP2_X, N, N, ALU_X, FU_ALU, N, WB_X, N, Y, MEM_NOP, SZ_X, CSR_X, N)
)
val decode_ops = ListLookup(io.instBundleIn.inst, dummy, decodeops)
val (inst_valid: Bool) :: br_Type :: op1Sel :: op2Sel :: (rs1Ren: Bool) :: (rs2Ren: Bool) :: aluOp :: fuType :: (isWordOp: Bool) :: wbSel :: (wbEn: Bool) :: (memEn: Bool) :: memOp :: memMask :: csrOp :: (isFence: Bool) :: Nil = decode_ops
Expand All @@ -161,7 +184,8 @@ class Decode extends Module {
IMM_UTYPE -> extractImm(new UTypeInstruction),
IMM_JTYPE -> extractImm(new JTypeInstruction),
IMM_BTYPE -> extractImm(new BTypeInstruction),
IMM_ZEXT -> extractImm(new CSRIInstruction)
IMM_ZEXT -> extractImm(new CSRIInstruction),
IMM_ZERO -> 0.U
))
io.decode2Exe.instValid := inst_valid & io.instBundleIn.instValid
io.decode2Exe.BrType := br_Type
Expand Down
21 changes: 14 additions & 7 deletions src/main/scala/core/exu.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,13 +101,20 @@ class EXU extends Module {
val mem = Module(new MEM)
io.toclint <> mem.io.toclint
io.mem2dmem <> mem.io.mem2dmem
mem.io.MemType := io.decode2Exe.MemType
mem.io.isMemOp := io.decode2Exe.isMemOp & io.instBundleIn.instValid
mem.io.MemOp := io.decode2Exe.MemOp
mem.io.baseAddr := op1
mem.io.imm := op2
mem.io.R2Val := io.decode2Exe.R2val
mem.io.exceInfoIn := io.decode2Exe.exceInfo
// TODO: a real MMU
mem.io.mem2mmu.respPAddr := mem.io.mem2mmu.reqVAddr - 0x80000000L.U
mem.io.mem2mmu.respValid := true.B
mem.io.mem2mmu.respPageFault := false.B

mem.io.instPC := io.instBundleIn.inst_pc
mem.io.MemType := io.decode2Exe.MemType
mem.io.fuOp := io.decode2Exe.ALUOp
mem.io.isMemOp := io.decode2Exe.isMemOp & io.instBundleIn.instValid
mem.io.MemOp := io.decode2Exe.MemOp
mem.io.baseAddr := op1
mem.io.imm := op2
mem.io.R2Val := io.decode2Exe.R2val
mem.io.exceInfoIn := io.decode2Exe.exceInfo
io.exe2Commit.memResult := mem.io.memResult

io.pauseReq := divu.io.divBusy || mulu.io.mulBusy || mem.io.pauseReq
Expand Down
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