Add reset logic to prevent 'X'

Bohan-hu · Dec 5, 2020 · 4c6dbe0 · 4c6dbe0
1 parent 70d8b81
commit 4c6dbe0
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Showing 3 changed files with 7 additions and 3 deletions.
diff --git a/src/main/scala/core/regfile.scala b/src/main/scala/core/regfile.scala
@@ -44,6 +44,10 @@ class Regfile extends Module {
   when(io.wrPort.wen & io.wrPort.waddr.orR) {
     Regs(io.wrPort.waddr) := io.wrPort.wdata
   }
+  when(reset.asBool()) {
+    for (i <- 0 until 8)
+        Regs(i) := 0.U
+  }
   BoringUtils.addSource(VecInit((0 to 31).map(i => Regs(i))), "difftestRegs")
 }
 

diff --git a/src/main/scala/mmu/tlb.scala b/src/main/scala/mmu/tlb.scala
@@ -76,8 +76,8 @@ class TLB extends Module{
         }
       }
     }
-    when(io.flush) {
-      tlbRegs(i).valid := false.B
+    when(io.flush | reset.asBool()) {
+      tlbRegs(i) := 0.U.asTypeOf(new TLBEntry)
     }
   }
 }

diff --git a/src/main/scala/sim/axiram.scala b/src/main/scala/sim/axiram.scala
@@ -87,7 +87,7 @@ class AXI_ram extends BlackBox with HasBlackBoxInline {
     // Width of ID signal
     parameter ID_WIDTH = 4,
     // Extra pipeline register on output
-    parameter PIPELINE_OUTPUT = 0
+    parameter PIPELINE_OUTPUT = 1
 )
 (
     input  wire                   clock,