update remove blank wires to keep classical bits

pytket/binders/circuit/Circuit/main.cpp

@@ -431,7 +431,9 @@ void def_circuit(py::class_<Circuit, std::shared_ptr<Circuit>> &pyCircuit) {
           "from the circuit. This may occur when optimisations "
           "recognise that the operations on a qubit reduce to the "
           "identity, or when routing adds wires to \"fill out\" the "
-          "architecture.")
+          "architecture.\n\n:param remove_classical_wire: select if "
+          "empty classical wires should be removed, too",
+          py::arg("remove_classical_wire"))
       .def(
           "add_blank_wires", &Circuit::add_blank_wires,
           "Adds a number of new qubits to the circuit. These will be "

pytket/conanfile.py

@@ -32,7 +32,7 @@ def package(self):
         cmake.install()
 
     def requirements(self):
-        self.requires("tket/1.3.2@tket/stable")
+        self.requires("tket/1.3.3@tket/stable")
         self.requires("tklog/0.3.3@tket/stable")
         self.requires("tkrng/0.3.3@tket/stable")
         self.requires("tkassert/0.3.4@tket/stable")

pytket/docs/changelog.rst

@@ -9,10 +9,12 @@ Features:
 * Add ``OpType.CnRx`` and ``OpType.CnRz``.
 * Add ``AutoRebase`` and ``AutoSquash`` passes.
   Deprecate ``auto_rebase_pass`` and ``auto_squash_pass``.
+* Add new parameter added to `remove_blank_wires` to allow to keep empty classical bits
 
 Fixes:
 
 * Allow barriers when dagger or transpose a circuit.
+* Keep blank classical wires when running `FlattenRelabelRegistersPass`
 
 
 1.28.0 (May 2024)

pytket/pytket/_tket/circuit.pyi

@@ -2263,9 +2263,11 @@ class Circuit:
         """
         Query whether a qubit has its final state discarded
         """
-    def remove_blank_wires(self) -> None:
+    def remove_blank_wires(self, remove_classical_wire: bool) -> None:
         """
         Removes any Input-Output pairs in the DAG with no intervening operations, i.e. removes untouched qubits/bits from the circuit. This may occur when optimisations recognise that the operations on a qubit reduce to the identity, or when routing adds wires to "fill out" the architecture.
+
+        :param remove_classical_wire: select if empty classical wires should be removed, too
         """
     def rename_units(self, map: dict[pytket._tket.unit_id.UnitID | pytket._tket.unit_id.Qubit | pytket._tket.unit_id.Bit, pytket._tket.unit_id.UnitID | pytket._tket.unit_id.Qubit | pytket._tket.unit_id.Bit]) -> bool:
         """

tket/conanfile.py

@@ -23,7 +23,7 @@
 
 class TketConan(ConanFile):
     name = "tket"
-    version = "1.3.2"
+    version = "1.3.3"
     package_type = "library"
     license = "Apache 2"
     homepage = "https://github.com/CQCL/tket"

tket/include/tket/Circuit/Circuit.hpp

@@ -762,8 +762,13 @@ class Circuit {
   // Basic Circuit Manipulation//
   //////////////////////////////
 
-  // O(V), `V` the number of vertices
-  void remove_blank_wires();
+  /**
+   * O(V), `V` the number of vertices
+   * removes all blank wires
+   * @param remove_classical_wire option to choose if empty classical wire
+   * should be removed as well
+   */
+  void remove_blank_wires(bool remove_classical_wire = true);
 
   /**
    * Remove all gates in the circuits that are identities

tket/src/Circuit/basic_circ_manip.cpp

@@ -32,20 +32,22 @@ namespace tket {
 // if there are any blank wires in the circuit,
 // this method removes them and removes the vertices
 // from boundaries
-void Circuit::remove_blank_wires() {
+void Circuit::remove_blank_wires(bool remove_classical_wire) {
   VertexList bin;
   unit_vector_t unused_units;
   const Op_ptr noop = get_op_ptr(OpType::noop);
   for (const BoundaryElement& el : boundary.get<TagID>()) {
-    Vertex in = el.in_;
-    Vertex out = el.out_;
-    VertexVec succs = get_successors(in);
-    if (succs.size() == 1 && succs.front() == out) {
-      dag[in].op = noop;
-      bin.push_back(in);
-      dag[out].op = noop;
-      bin.push_back(out);
-      unused_units.push_back(el.id_);
+    if (remove_classical_wire || el.type() == UnitType::Qubit) {
+      Vertex in = el.in_;
+      Vertex out = el.out_;
+      VertexVec succs = get_successors(in);
+      if (succs.size() == 1 && succs.front() == out) {
+        dag[in].op = noop;
+        bin.push_back(in);
+        dag[out].op = noop;
+        bin.push_back(out);
+        unused_units.push_back(el.id_);
+      }
     }
   }
   for (const UnitID& u : unused_units) {

tket/src/Predicates/PassGenerators.cpp

@@ -357,7 +357,7 @@ PassPtr gen_flatten_relabel_registers_pass(const std::string& label) {
   Transform t =
       Transform([=](Circuit& circuit, std::shared_ptr<unit_bimaps_t> maps) {
         unsigned n_qubits = circuit.n_qubits();
-        circuit.remove_blank_wires();
+        circuit.remove_blank_wires(false);
         bool changed = circuit.n_qubits() < n_qubits;
         std::map<Qubit, Qubit> relabelling_map;
         std::vector<Qubit> all_qubits = circuit.all_qubits();

tket/test/src/Circuit/test_Circ.cpp

@@ -1020,6 +1020,29 @@ SCENARIO(
   test.assert_valid();
 }
 
+SCENARIO(
+    "Test a circuit with blank wires can have the blank wires removed keeping "
+    "classical",
+    "[blank_wires]") {
+  Circuit test(4, 2);
+  test.add_op<unsigned>(OpType::CX, {0, 1});
+  test.add_op<unsigned>(OpType::Z, {0});
+
+  WHEN("Check Commands work correctly") {
+    std::vector<Command> coms = test.get_commands();
+    REQUIRE(*coms[0].get_op_ptr() == *get_op_ptr(OpType::CX));
+    REQUIRE(*coms[1].get_op_ptr() == *get_op_ptr(OpType::Z));
+  }
+
+  test.add_blank_wires(8);
+  int n = test.n_vertices();
+  test.remove_blank_wires(false);
+  int m = test.n_vertices();
+  REQUIRE(n == 30);
+  REQUIRE(m == 10);
+  test.assert_valid();
+}
+
 SCENARIO(
     "Test that the copy constructor and copy assignment operator work "
     "correctly",