update remove blank wires to keep classical bits #1435

cqc-melf · 2024-06-04T09:57:37Z

Description

Solves #1434

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Please mention any github issues addressed by this PR.

Checklist

I have performed a self-review of my code.
I have commented hard-to-understand parts of my code.
I have made corresponding changes to the public API documentation.
I have added tests that prove my fix is effective or that my feature works.
I have updated the changelog with any user-facing changes.

pytket/docs/changelog.rst

cqc-alec · 2024-06-05T12:30:44Z

tket/include/tket/Circuit/Circuit.hpp

+   * removes all blank wires
+   * @param remove_classical_wire option to choose if empty classical wire
+   * should be removed as well
+   */
+  void remove_blank_wires(bool remove_classical_wire = true);


I think it would be more intuitive to have a keep_blank_classical_wires argument that defaults to false.

done in 3b4bb6f

cqc-alec · 2024-06-05T12:31:50Z

pytket/binders/circuit/Circuit/main.cpp

-          "architecture.")
+          "architecture.\n\n:param remove_classical_wire: select if "
+          "empty classical wires should be removed, too",
+          py::arg("remove_classical_wire"))


Suggest having a keep_blank_classical_wires argument that defaults to false.

done in 3b4bb6f

Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com>

pytket/binders/circuit/Circuit/main.cpp

pytket/pytket/_tket/circuit.pyi

pytket/binders/circuit/Circuit/main.cpp

cqc-alec · 2024-06-05T15:16:00Z

tket/test/src/Circuit/test_Circ.cpp

+  test.add_blank_wires(8);
+  int n = test.n_vertices();
+  test.remove_blank_wires(true);
+  int m = test.n_vertices();
+  REQUIRE(n == 30);
+  REQUIRE(m == 10);
+  test.assert_valid();


I think a test that just checked the number of qubits and bits in the circuit rather than the number of vertices would be clearer, but no big deal.

I just copied that from the old testcase, happy to update both.

done in 7f09164

Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com>

* Allow barriers when dagger or transpose circuits (#1400) * Allow barriers in dagger() and transpose() * bump tket version * add changelog entry * Format test * Bump cachix/install-nix-action from 26 to 27 (#1403) Bumps [cachix/install-nix-action](https://github.com/cachix/install-nix-action) from 26 to 27. - [Release notes](https://github.com/cachix/install-nix-action/releases) - [Commits](cachix/install-nix-action@v26...V27) --- updated-dependencies: - dependency-name: cachix/install-nix-action dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Bump actions/add-to-project from 0.6.1 to 1.0.1 (#1404) Bumps [actions/add-to-project](https://github.com/actions/add-to-project) from 0.6.1 to 1.0.1. - [Release notes](https://github.com/actions/add-to-project/releases) - [Commits](actions/add-to-project@v0.6.1...v1.0.1) --- updated-dependencies: - dependency-name: actions/add-to-project dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Use `ubuntu-24.04` on CI (#1401) * Add OpType.CnRx and OpType.CnRz (#1405) * Add CnRx and CnRz * Update circuit_test.py * re clang format * regen stubs * Update changelog.rst * bump version * Unbump changelog... oops * Update ControlledGates.cpp * split controlled phase gate decomp * Update circuit_test.py * Update OpType.hpp * Update `place_fully_connected` (#1409) * update place_fully_connected * Update placement.cpp * Update placement_test.py * Bump cachix/cachix-action from 14 to 15 (#1416) Bumps [cachix/cachix-action](https://github.com/cachix/cachix-action) from 14 to 15. - [Release notes](https://github.com/cachix/cachix-action/releases) - [Commits](cachix/cachix-action@v14...v15) --- updated-dependencies: - dependency-name: cachix/cachix-action dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Post benchmarking results to slack (#1417) * Post results to slack * Remove run on PR * Remove documentation * Remove pr comment * Refactor auto rebase and auto squash (#1410) * Implement python rebase functions in C++ * Implement auto_rebase in c++ * Implement auto_squash in c++ * Test exception handling * Add AutoRebase, AutoSquash to binder * Update circuit_library * Update json schema * deprecate auto_rebase and auto_squash * Fix bug * Replace auto_rebase_pass and auto_squash_pass with AutoRebase and AutoSquash * Remove auto_rebase_pass and auto_squash_pass from docs * Bump tket version * Remove extra lines in docs * Regenerate stubs * Add changelog entry * Fix linting errors * Sorted gate sets in serialisation * Better deprecation handling * Add docs for added CircPool functions * Add comment to hard-to-understand test * Fix typo in json schema * Replace `find()` with `contains()` * Set `always_squash_symbols` to false when squash `Rz` and `PhasedX` * Revert to using ubuntu-22.04 runner for valgrind checks. (#1432) * Handle `NPhasedX` gates in `decompose_cliffords_std()` (#1431) * Add workflow to mark stale issues and PRs. (#1437) * update remove blank wires to keep classical bits (#1435) * update remove blank wires * add testcase * update changelog * update tket version * update testcases * update regen stubs * fix typo * add param to remove_classical_wire in python * regen stubs * Update pytket/docs/changelog.rst Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * rename parameter to keep_blank_classical_wires * update tket version * fix param * Update pytket/binders/circuit/Circuit/main.cpp Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Update pytket/binders/circuit/Circuit/main.cpp Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Update pytket/pytket/_tket/circuit.pyi Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * update testcases to use bits and qubits * regen stubs --------- Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Try running ZX test with all Python versions. (#1438) * Update Windows compiler version. (#1442) * Fix FlattenRelabelRegistersPass (#1441) * update tket version * update parameter of remove_blank_wires in gen_flatten_relabel_registers_pass * add python testcase for compilation pass flatten_relabel * update tket version * Allow classical transforms and predicates on up to 64 bits (#1446) * Update docs and changelog for 1.29.0 release. (#1447) --------- Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: yao-cqc <75305462+yao-cqc@users.noreply.github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> Co-authored-by: Silas Dilkes <36165522+sjdilkes@users.noreply.github.com> Co-authored-by: Dan Mills <52407433+daniel-mills-cqc@users.noreply.github.com> Co-authored-by: cqc-melf <70640934+cqc-melf@users.noreply.github.com>

* Allow barriers when dagger or transpose circuits (#1400) * Allow barriers in dagger() and transpose() * bump tket version * add changelog entry * Format test * Bump cachix/install-nix-action from 26 to 27 (#1403) Bumps [cachix/install-nix-action](https://github.com/cachix/install-nix-action) from 26 to 27. - [Release notes](https://github.com/cachix/install-nix-action/releases) - [Commits](cachix/install-nix-action@v26...V27) --- updated-dependencies: - dependency-name: cachix/install-nix-action dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Bump actions/add-to-project from 0.6.1 to 1.0.1 (#1404) Bumps [actions/add-to-project](https://github.com/actions/add-to-project) from 0.6.1 to 1.0.1. - [Release notes](https://github.com/actions/add-to-project/releases) - [Commits](actions/add-to-project@v0.6.1...v1.0.1) --- updated-dependencies: - dependency-name: actions/add-to-project dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Use `ubuntu-24.04` on CI (#1401) * Add OpType.CnRx and OpType.CnRz (#1405) * Add CnRx and CnRz * Update circuit_test.py * re clang format * regen stubs * Update changelog.rst * bump version * Unbump changelog... oops * Update ControlledGates.cpp * split controlled phase gate decomp * Update circuit_test.py * Update OpType.hpp * Update `place_fully_connected` (#1409) * update place_fully_connected * Update placement.cpp * Update placement_test.py * Bump cachix/cachix-action from 14 to 15 (#1416) Bumps [cachix/cachix-action](https://github.com/cachix/cachix-action) from 14 to 15. - [Release notes](https://github.com/cachix/cachix-action/releases) - [Commits](cachix/cachix-action@v14...v15) --- updated-dependencies: - dependency-name: cachix/cachix-action dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Post benchmarking results to slack (#1417) * Post results to slack * Remove run on PR * Remove documentation * Remove pr comment * Refactor auto rebase and auto squash (#1410) * Implement python rebase functions in C++ * Implement auto_rebase in c++ * Implement auto_squash in c++ * Test exception handling * Add AutoRebase, AutoSquash to binder * Update circuit_library * Update json schema * deprecate auto_rebase and auto_squash * Fix bug * Replace auto_rebase_pass and auto_squash_pass with AutoRebase and AutoSquash * Remove auto_rebase_pass and auto_squash_pass from docs * Bump tket version * Remove extra lines in docs * Regenerate stubs * Add changelog entry * Fix linting errors * Sorted gate sets in serialisation * Better deprecation handling * Add docs for added CircPool functions * Add comment to hard-to-understand test * Fix typo in json schema * Replace `find()` with `contains()` * Set `always_squash_symbols` to false when squash `Rz` and `PhasedX` * Revert to using ubuntu-22.04 runner for valgrind checks. (#1432) * Handle `NPhasedX` gates in `decompose_cliffords_std()` (#1431) * Add workflow to mark stale issues and PRs. (#1437) * update remove blank wires to keep classical bits (#1435) * update remove blank wires * add testcase * update changelog * update tket version * update testcases * update regen stubs * fix typo * add param to remove_classical_wire in python * regen stubs * Update pytket/docs/changelog.rst Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * rename parameter to keep_blank_classical_wires * update tket version * fix param * Update pytket/binders/circuit/Circuit/main.cpp Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Update pytket/binders/circuit/Circuit/main.cpp Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Update pytket/pytket/_tket/circuit.pyi Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * update testcases to use bits and qubits * regen stubs --------- Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Try running ZX test with all Python versions. (#1438) * Update Windows compiler version. (#1442) * Fix FlattenRelabelRegistersPass (#1441) * update tket version * update parameter of remove_blank_wires in gen_flatten_relabel_registers_pass * add python testcase for compilation pass flatten_relabel * update tket version * Allow classical transforms and predicates on up to 64 bits (#1446) * Update docs and changelog for 1.29.0 release. (#1447) * Update MultiplexedTensoredU2Box Circuit Construction (#1443) * First changes, compiling but returning incorrect results * MultiplexedU2Box construction working * hmm * refactor to separate * Update Multiplexor.cpp * Working on specific cases * Update test_Multiplexor.cpp * Update test_Multiplexor.cpp * working on most cases ... * Refactor into separate methods * refactor again and neaten code up * Tidied, failling test for mystery reasons, moving on ... * Multiplexed-rz with interleaved gates * Tidy for PR * bump * Update Multiplexor.hpp * Update Multiplexor.hpp * Update test_Multiplexor.cpp * Update Multiplexor.cpp * attempt to remove mismatch ?? * Update Multiplexor.cpp * Update Multiplexor.cpp * fix * changes * update rz rotation indexing * add asserts * update error threshold * add multiple constructors * bump * Update changelog.rst * Revert switch from 32- to 64-bit maximum width (#1449) * Update docs and changelog for 1.29.1 release. (#1451) * Revert to removing blank classical wires in `FlattenRelabelRegistersPass` (#1453) * Update docs and changelog for 1.29.2 release. (#1454) * remove space --------- Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: yao-cqc <75305462+yao-cqc@users.noreply.github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> Co-authored-by: Silas Dilkes <36165522+sjdilkes@users.noreply.github.com> Co-authored-by: Dan Mills <52407433+daniel-mills-cqc@users.noreply.github.com> Co-authored-by: cqc-melf <70640934+cqc-melf@users.noreply.github.com>

cqc-melf added 4 commits June 4, 2024 10:50

update remove blank wires

b3e1b4f

add testcase

26434e9

update changelog

95e0431

update tket version

d40982f

cqc-melf changed the title ~~Melf/update remove blank wires~~ update remove blank wires to keep classical bits Jun 4, 2024

update testcases

d3690cc

CalMacCQ reviewed Jun 4, 2024

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cqc-melf and others added 5 commits June 4, 2024 17:52

update regen stubs

02aa266

fix typo

937af3b

Merge branch 'main' into melf/update-remove-blank-wires

99e8548

add param to remove_classical_wire in python

522943e

regen stubs

89cd622

cqc-melf marked this pull request as ready for review June 5, 2024 09:13

cqc-melf requested a review from cqc-alec June 5, 2024 09:13

cqc-alec reviewed Jun 5, 2024

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cqc-melf and others added 5 commits June 5, 2024 14:46

Update pytket/docs/changelog.rst

a616e9f

Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com>

rename parameter to keep_blank_classical_wires

3b4bb6f

Merge branch 'main' into melf/update-remove-blank-wires

09c0328

update tket version

fcda567

fix param

77cd431

cqc-melf requested a review from cqc-alec June 5, 2024 14:52

cqc-alec reviewed Jun 5, 2024

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cqc-melf and others added 5 commits June 5, 2024 17:23

Update pytket/binders/circuit/Circuit/main.cpp

a68b692

Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com>

Update pytket/binders/circuit/Circuit/main.cpp

6ec659e

Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com>

Update pytket/pytket/_tket/circuit.pyi

14c8619

Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com>

update testcases to use bits and qubits

7f09164

regen stubs

6d03ecf

cqc-melf requested a review from cqc-alec June 5, 2024 18:21

cqc-alec approved these changes Jun 6, 2024

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cqc-melf merged commit 02ddc13 into main Jun 6, 2024
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cqc-melf deleted the melf/update-remove-blank-wires branch June 6, 2024 07:43

cqc-melf mentioned this pull request Jun 7, 2024

Fix FlattenRelabelRegistersPass #1441

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CalMacCQ mentioned this pull request Jun 17, 2024

FlattenRelabelRegistersPass removes blank classical wires #1434

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update remove blank wires to keep classical bits #1435

update remove blank wires to keep classical bits #1435

cqc-melf commented Jun 4, 2024 •

edited

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update remove blank wires to keep classical bits #1435

update remove blank wires to keep classical bits #1435

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cqc-melf commented Jun 4, 2024 • edited Loading

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cqc-melf commented Jun 4, 2024 •

edited

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