Update MultiplexedTensoredU2Box Circuit Construction #1443

sjdilkes · 2024-06-07T15:32:19Z

By interleaving the {CX,U1} and {CX, Rz} subcircuits comprising the MultiplexedTensoredU2Box Circuit construction, we can improve the Circuit depth without changing the number of gates.

This PR updates the MultiplexedRotationBox::decompose and MultiplexedU2Box::decompose methods to return, essentially, lists of relevant commands instead of modifying a Circuit object passed by reference.

For MultiplexedRotationBox::generate_circuit and MultiplexedU2Box::generate_circuit a Circuit object is constructed by iterating through these commands and adding to a Circuit object.

In MultiplexedTensoredU2Box, the construction is broken down into a series of MultiplexedU2Box, each synthesised separately. Now, when these new lists are returned from decompose, by synthesising each MultiplexedU2Box individually, the gates at the same index for each list are added at the same time. Additionally, the control conditions for each MultiplexedU2Box are permuted s.t. the order of CX gates for the {CX,U1} and {CX, Rz} subcircuits can differ between each construction.

N.B. This is a draft PR as there are a couple of edge cases that generate the wrong unitary that I can't pinpoint the issue with. I thought some time and placating the CI might help me clock the issue. *I wasn't initialising a float to 0 and an error threshold was too high.

Checklist

I have performed a self-review of my code.
I have commented hard-to-understand parts of my code.
I have made corresponding changes to the public API documentation.
I have added tests that prove my fix is effective or that my feature works.
I have updated the changelog with any user-facing changes.

yao-cqc · 2024-06-13T12:41:51Z

tket/include/tket/Circuit/Multiplexor.hpp

@@ -96,6 +96,22 @@ class MultiplexorBox : public Box {
  ctrl_op_map_t op_map_;
 };

+struct GateSpec {
+  // TODO: this struct is a little confused as only CX needs qubit, only


Perhaps we can have three constructors?

Yeah that makes so much more sense - will do it

yao-cqc · 2024-06-14T13:14:16Z

tket/src/Circuit/Multiplexor.cpp

+          // we also need to map gate.qubit to the correct qubit
+          // we know that the bitstrings for the "target"th target have been
+          // left rotated by "target", so:
+          rotated_index = (*gate.qubit + (target % n_targets_)) % n_controls_;


I'm a little confused by this...

yao-cqc · 2024-06-14T13:23:55Z

tket/src/Circuit/Multiplexor.cpp

+  return;
+}
+
+Eigen::VectorXcd combine_diagonals(


Can you explain how this rotate works?

yao-cqc

Looks good! Just need to bump the tket lib version

* Allow barriers when dagger or transpose circuits (#1400) * Allow barriers in dagger() and transpose() * bump tket version * add changelog entry * Format test * Bump cachix/install-nix-action from 26 to 27 (#1403) Bumps [cachix/install-nix-action](https://github.com/cachix/install-nix-action) from 26 to 27. - [Release notes](https://github.com/cachix/install-nix-action/releases) - [Commits](cachix/install-nix-action@v26...V27) --- updated-dependencies: - dependency-name: cachix/install-nix-action dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Bump actions/add-to-project from 0.6.1 to 1.0.1 (#1404) Bumps [actions/add-to-project](https://github.com/actions/add-to-project) from 0.6.1 to 1.0.1. - [Release notes](https://github.com/actions/add-to-project/releases) - [Commits](actions/add-to-project@v0.6.1...v1.0.1) --- updated-dependencies: - dependency-name: actions/add-to-project dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Use `ubuntu-24.04` on CI (#1401) * Add OpType.CnRx and OpType.CnRz (#1405) * Add CnRx and CnRz * Update circuit_test.py * re clang format * regen stubs * Update changelog.rst * bump version * Unbump changelog... oops * Update ControlledGates.cpp * split controlled phase gate decomp * Update circuit_test.py * Update OpType.hpp * Update `place_fully_connected` (#1409) * update place_fully_connected * Update placement.cpp * Update placement_test.py * Bump cachix/cachix-action from 14 to 15 (#1416) Bumps [cachix/cachix-action](https://github.com/cachix/cachix-action) from 14 to 15. - [Release notes](https://github.com/cachix/cachix-action/releases) - [Commits](cachix/cachix-action@v14...v15) --- updated-dependencies: - dependency-name: cachix/cachix-action dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> * Post benchmarking results to slack (#1417) * Post results to slack * Remove run on PR * Remove documentation * Remove pr comment * Refactor auto rebase and auto squash (#1410) * Implement python rebase functions in C++ * Implement auto_rebase in c++ * Implement auto_squash in c++ * Test exception handling * Add AutoRebase, AutoSquash to binder * Update circuit_library * Update json schema * deprecate auto_rebase and auto_squash * Fix bug * Replace auto_rebase_pass and auto_squash_pass with AutoRebase and AutoSquash * Remove auto_rebase_pass and auto_squash_pass from docs * Bump tket version * Remove extra lines in docs * Regenerate stubs * Add changelog entry * Fix linting errors * Sorted gate sets in serialisation * Better deprecation handling * Add docs for added CircPool functions * Add comment to hard-to-understand test * Fix typo in json schema * Replace `find()` with `contains()` * Set `always_squash_symbols` to false when squash `Rz` and `PhasedX` * Revert to using ubuntu-22.04 runner for valgrind checks. (#1432) * Handle `NPhasedX` gates in `decompose_cliffords_std()` (#1431) * Add workflow to mark stale issues and PRs. (#1437) * update remove blank wires to keep classical bits (#1435) * update remove blank wires * add testcase * update changelog * update tket version * update testcases * update regen stubs * fix typo * add param to remove_classical_wire in python * regen stubs * Update pytket/docs/changelog.rst Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * rename parameter to keep_blank_classical_wires * update tket version * fix param * Update pytket/binders/circuit/Circuit/main.cpp Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Update pytket/binders/circuit/Circuit/main.cpp Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Update pytket/pytket/_tket/circuit.pyi Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * update testcases to use bits and qubits * regen stubs --------- Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> * Try running ZX test with all Python versions. (#1438) * Update Windows compiler version. (#1442) * Fix FlattenRelabelRegistersPass (#1441) * update tket version * update parameter of remove_blank_wires in gen_flatten_relabel_registers_pass * add python testcase for compilation pass flatten_relabel * update tket version * Allow classical transforms and predicates on up to 64 bits (#1446) * Update docs and changelog for 1.29.0 release. (#1447) * Update MultiplexedTensoredU2Box Circuit Construction (#1443) * First changes, compiling but returning incorrect results * MultiplexedU2Box construction working * hmm * refactor to separate * Update Multiplexor.cpp * Working on specific cases * Update test_Multiplexor.cpp * Update test_Multiplexor.cpp * working on most cases ... * Refactor into separate methods * refactor again and neaten code up * Tidied, failling test for mystery reasons, moving on ... * Multiplexed-rz with interleaved gates * Tidy for PR * bump * Update Multiplexor.hpp * Update Multiplexor.hpp * Update test_Multiplexor.cpp * Update Multiplexor.cpp * attempt to remove mismatch ?? * Update Multiplexor.cpp * Update Multiplexor.cpp * fix * changes * update rz rotation indexing * add asserts * update error threshold * add multiple constructors * bump * Update changelog.rst * Revert switch from 32- to 64-bit maximum width (#1449) * Update docs and changelog for 1.29.1 release. (#1451) * Revert to removing blank classical wires in `FlattenRelabelRegistersPass` (#1453) * Update docs and changelog for 1.29.2 release. (#1454) * remove space --------- Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: yao-cqc <75305462+yao-cqc@users.noreply.github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Co-authored-by: Alec Edgington <54802828+cqc-alec@users.noreply.github.com> Co-authored-by: Silas Dilkes <36165522+sjdilkes@users.noreply.github.com> Co-authored-by: Dan Mills <52407433+daniel-mills-cqc@users.noreply.github.com> Co-authored-by: cqc-melf <70640934+cqc-melf@users.noreply.github.com>

sjdilkes added 28 commits June 5, 2024 19:22

First changes, compiling but returning incorrect results

aed780c

MultiplexedU2Box construction working

65aa52d

hmm

fb52395

refactor to separate

d0f754c

Update Multiplexor.cpp

43819af

Working on specific cases

a84089e

Update test_Multiplexor.cpp

5d437b2

Update test_Multiplexor.cpp

ac9b9c3

working on most cases ...

5837219

Refactor into separate methods

cc3ad6e

refactor again and neaten code up

80b9636

Tidied, failling test for mystery reasons, moving on ...

9ff6d30

Multiplexed-rz with interleaved gates

d050849

Tidy for PR

26929b2

Merge branch 'main' into interleave-multiplexed-u2-mrz

4afb301

bump

aa7aa27

Update Multiplexor.hpp

6f35478

Update Multiplexor.hpp

e44f3a5

Update test_Multiplexor.cpp

fd6f868

Update Multiplexor.cpp

7009f12

attempt to remove mismatch ??

72e6658

Update Multiplexor.cpp

0e11c2f

Update Multiplexor.cpp

e059c30

fix

ceadd8c

changes

e62183b

update rz rotation indexing

4dc27d5

add asserts

32a4cd5

update error threshold

97f71df

sjdilkes requested a review from yao-cqc June 10, 2024 16:57

sjdilkes marked this pull request as ready for review June 10, 2024 16:57

yao-cqc reviewed Jun 14, 2024

View reviewed changes

sjdilkes requested a review from yao-cqc June 14, 2024 16:14

sjdilkes added 2 commits June 14, 2024 17:23

add multiple constructors

c69159a

Merge branch 'main' into interleave-multiplexed-u2-mrz

bac9282

yao-cqc previously approved these changes Jun 17, 2024

View reviewed changes

bump

f1821dc

sjdilkes dismissed yao-cqc’s stale review via f1821dc June 17, 2024 09:20

Update changelog.rst

1787044

sjdilkes requested a review from yao-cqc June 17, 2024 09:54

yao-cqc approved these changes Jun 17, 2024

View reviewed changes

sjdilkes merged commit 8f10936 into main Jun 17, 2024
32 checks passed

sjdilkes deleted the interleave-multiplexed-u2-mrz branch June 17, 2024 09:56

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Update MultiplexedTensoredU2Box Circuit Construction #1443

Update MultiplexedTensoredU2Box Circuit Construction #1443

sjdilkes commented Jun 7, 2024 •

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Update MultiplexedTensoredU2Box Circuit Construction #1443

Update MultiplexedTensoredU2Box Circuit Construction #1443

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sjdilkes commented Jun 7, 2024 • edited Loading

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sjdilkes commented Jun 7, 2024 •

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