fix #75 vadbad scope probe on writeback

SpinalHDL · Jan 15, 2024 · c2cbc58 · c2cbc58
1 parent b312da8
commit c2cbc58
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/main/scala/naxriscv/platform/litex/NaxSoc.scala b/src/main/scala/naxriscv/platform/litex/NaxSoc.scala
@@ -189,7 +189,7 @@ class NaxSoc(c : NaxSocConfig) extends Component{
           case p: FetchCachePlugin => add(p.logic.refill.fire, i * 0x80 + 0x000)
           case p: DataCachePlugin => {
             add(p.logic.cache.refill.push.fire, i * 0x80 + 0x010)
-            add(p.logic.cache.writeback.push.fire, i * 0x80 + 0x014)
+            add(p.logic.cache.writeback.push.fire && p.logic.cache.writeback.push.dirty, i * 0x80 + 0x014)
             if (withL2) {
               val l2c = l2.cache.logic.cache
               l2c.rework {

diff --git a/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala b/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
@@ -112,7 +112,7 @@ object SocSim extends App {
           case p: FetchCachePlugin => add(p.logic.refill.fire, i * 0x80 + 0x000)
           case p: DataCachePlugin => {
             add(p.logic.cache.refill.push.fire, i * 0x80 + 0x010)
-            add(p.logic.cache.writeback.push.fire, i * 0x80 + 0x014)
+            add(p.logic.cache.writeback.push.fire && p.logic.cache.writeback.push.dirty, i * 0x80 + 0x014)
             if (withL2) {
               val l2c = l2.cache.logic.cache
               l2c.rework{